CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 3

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
USB Interface
EZ-OTG has two built-in Host/Peripheral SIEs that each have
a single USB transceiver, meeting the USB 2.0 specification
requirements for full and low speed (high speed is not support-
ed). In Host mode, EZ-OTG supports two downstream ports;
each supports control, interrupt, bulk, and isochronous trans-
fers. In Peripheral mode, EZ-OTG supports one peripheral
port with eight endpoints for each of the two SIEs. Endpoint 0
is dedicated as the control endpoint and only supports control
transfers. Endpoints 1 though 7 support Interrupt, bulk (up to
64 bytes per packet), or isochronous transfers (up to 1023
bytes per packet size). EZ-OTG also supports a combination
of Host and Peripheral ports simultaneously, as shown in
Table
Table 2. USB Port Configuration Options
USB Features
USB Pins
Table 3. USB Interface Pins
OTG
OTG + 1 Host
OTG + 1 Peripheral
1 Host + 1 Peripheral
1 Host + 1 Peripheral
2 Hosts
1 Host
1 Host
2 Peripherals
1 Peripheral
1 Peripheral
DM1A
DP1A
DM2A
DP2A
• USB 2.0 compatible for full and low speed
• Up to two downstream USB host ports
• Up to two upstream USB peripheral ports
• Configurable endpoint buffers (pointer and length), must
• Up to eight available peripheral endpoints (1 control
• Supports Control, Interrupt, Bulk, and Isochronous transfers
• Internal DMA channels for each endpoint
• Internal pull up and pull down resistors
• Internal Series termination resistors on USB data lines
reside in internal RAM
endpoint)
Port Configurations
2.
Pin Name
Peripheral
Peripheral
Peripheral
Port 1A
OTG
OTG
OTG
Host
Host
Host
–
–
Pin Number
C2
D3
F2
E3
Peripheral
Peripheral
Peripheral
Peripheral
Port 2A
Host
Host
Host
Host
–
–
–
OTG Interface
EZ-OTG has one USB port that is compatible with the USB
On-The-Go supplement to the USB 2.0 specification. The USB
OTG port has various hardware features to support Session
Request Protocol (SRP) and Host Negotiation Protocol (HNP).
OTG is only supported on USB PORT 1A.
OTG Features
OTG Pins
Table 4. OTG Interface Pins
General Purpose IO Interface
EZ-OTG has up to 25 GPIO signals available. Several other
optional interfaces use GPIO pins as well and may reduce the
overall number of available GPIOs.
GPIO Description
All Inputs are sampled asynchronously with state changes oc-
curring at a rate of up to two 48 MHz clock cycles. GPIO pins
are latched directly into registers, a single flip-flop.
Unused Pin Descriptions
Unused USB pins must be tri-stated with the D+ line pulled
high through the internal pull-up resistor and the D– line pulled
low through the internal pull-down resistor.
Unused GPIO pins must be configured as outputs and driven
low.
UART Interface
EZ-OTG has a built-in UART interface. The UART interface
supports data rates from 900 to 115.2K baud. It can be used
as a development port or for other interface requirements. The
UART interface is exposed through GPIO pins.
DM1A
DP1A
OTGVBUS
OTGID
CSwitchA
CSwitchB
• Internal Charge Pump to supply and control VBUS
• VBUS Valid Status (above 4.4V)
• VBUS Status for 2.4V < VBUS < 0.8V
• ID Pin Status
• Switchable 2-Kohm internal discharge resistor on VBUS
• Switchable 500-ohm internal pull-up resistor on VBUS
• Individually switchable internal pull-up and pull-down
resistors on the USB data lines
Pin Name
Pin Number
CY7C67200
F2
E3
C1
F4
D1
D2
Page 3 of 78
[+] Feedback