CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 68

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
Clock Timing
I
f
v
t
t
t
t
t
Duty Cycle
f
t
t
t
t
t
t
t
t
t
t
t
t
Note
2
CLK
CLK
HIGH
LOW
RISE
FALL
SCL
LOW
HIGH
AA
BUF
HD.STA
SU.STA
HD.DAT
SU.DAT
R
F
SU.STO
DH
10.
XINH
C EEPROM Timing
Parameter
v
Parameter
XINH is required to be 3.0V to obtain an internal 50/50 duty cycle clock.
SDA OUT
[10]
SDA IN
1. I2C EEPROM Bus Timing - Serial I/O
SCL
Clock Frequency
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Bus Idle Before New Transmission
Start Hold Time
Start Setup Time
Data In Hold Time
Data In Setup Time
Input Rise Time
Input Fall Time
Stop Setup Time
Data Out Hold Time
t
SU.STA
XTALIN
Clock Frequency
Clock Input High
(XTALOUT left floating)
Clock Period
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
Description
t
HIGH
t
HD.STA
t
t
CLK
AA
Description
t
LOW
Clock Timing
t
HD.DAT
83.17
Min.
1.5
36
36
45
t
DH
t
t
t
FALL
HIGH
LOW
t
SU.DAT
1300
1300
Min.
600
900
600
600
100
600
83.33
Typ.
12.0
0
0
3.0
t
R
Typical
t
RISE
t
F
Max.
83.5
3.6
5.0
5.0
44
44
55
Max.
400
300
300
t
SU.STO
CY7C67200
Page 68 of 78
t
BUF
MHz
Unit
ns
ns
ns
ns
ns
%
V
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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