CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 33

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
Device n Endpoint n Count Result Register [R/W]
Register Description
The Device n Endpoint n Count Result register contains the
size difference in bytes between the Endpoint Count specified
in the Device n Endpoint n Count register and the last packet
received. If an overflow or underflow condition occurs, that is
the received packet length differs from the value specified in
the Device n Endpoint n Count register, the Length Exception
Flag bit in the Device n Endpoint n Status register will be set.
The value in this register is only considered when the Length
Exception Flag bit is set and the Error Flag bit is not set; both
bits are in the Device n Endpoint n Status register.
The Device n Endpoint n Count Result register is a memory
based register that must be initialized to 0x0000 before USB
Device operations are initiated. After initialization, this register
must not be written to again.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
• Device n Endpoint 0 Count Result Register [Device 1: 0x0208 Device 2: 0x0288]
• Device n Endpoint 1 Count Result Register [Device 1: 0x0218 Device 2: 0x0298]
• Device n Endpoint 2 Count Result Register [Device 1: 0x0228 Device 2: 0x02A8]
• Device n Endpoint 3 Count Result Register [Device 1: 0x0238 Device 2: 0x02B8]
• Device n Endpoint 4 Count Result Register [Device 1: 0x0248 Device 2: 0x02C8]
• Device n Endpoint 5 Count Result Register [Device 1: 0x0258 Device 2: 0x02D8]
• Device n Endpoint 6 Count Result Register [Device 1: 0x0268 Device 2: 0x02E8]
• Device n Endpoint 7 Count Result Register [Device 1: 0x0278 Device 2: 0x02F8]
R/W
R/W
15
X
X
7
R/W
R/W
14
X
6
X
Figure 34. Device n Endpoint n Count Result Register
R/W
R/W
13
X
X
5
R/W
R/W
12
X
X
4
Result (Bits [15:0])
The Result field contains the differences in bytes between the
received packet and the value specified in the Device n
Endpoint n Count register. If an overflow condition occurs,
Result [15:10] is set to ‘111111’, a 2’s complement value
indicating the additional byte count of the received packet. If
an underflow condition occurs, Result [15:0] indicates the
excess byte count (number of bytes not used).
Reserved
All reserved bits must be written as ‘0’.
...Result
Result...
R/W
R/W
11
X
X
3
R/W
R/W
10
X
X
2
R/W
R/W
1
X
X
9
CY7C67200
Page 33 of 78
R/W
R/W
X
0
X
8
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