CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 8

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
Minimum Hardware Requirements for Standalone Mode – Peripheral Only
Power Savings and Reset Description
The EZ-OTG modes and reset conditions are described in this
section.
Power Savings Mode Description
EZ-OTG has one main power savings mode, Sleep. For
detailed information on Sleep mode;
Sleep mode is used for USB applications to support USB
suspend and non USB applications as the main chip power
down mode.
In addition, EZ-OTG is capable of slowing down the CPU clock
speed through the CPU Speed register [0xC008] without
affecting other peripheral timing. Reducing the CPU clock
speed from 48 MHz to 24 MHz reduces the overall current
draw by around 8 mA while reducing it from 48 MHz to 3 MHz
reduces the overall current draw by approximately 15 mA.
*Bootloading begins after POR + 3ms BIOS bootup
*GPIO[31:30]
Up to 2k x8
>2k x8 to 64k x8
GND
Standard-B
or Mini-B
A0
A1
A2
Figure 5. Minimum Standalone Hardware Configuration – Peripheral Only
Up to 64k x8
EEPROM
SCL SDA
SDA SCL
31
SHIELD
VBus
D+
D-
GND
See section
30
VCC
WP
SCL
SDA
VCC
Vcc
10k
Bootstrap Options
Vcc
“Sleep”.
VReg
10k
Bootloading Firmware
GPIO[30]
GPIO[31]
VCC, AVCC,
BoostVCC
DPlus
DMinus
SCL*
SDA*
Reserved
GND, AGND,
BoostGND
Sleep
Sleep mode is the main chip power down mode and is also
used for USB suspend. Sleep mode is entered by setting the
Sleep Enable (bit 1) of the Power Control register [0xC00A].
During Sleep mode (USB Suspend) the following events and
states are true:
• GPIO pins maintain their configuration during sleep (in
• External Memory Address pins are driven low.
• XTALOUT is turned off.
• Internal PLL is turned off.
• Firmware must disable the charge pump (OTG Control
• Booster circuit is turned off.
• USB transceivers is turned off.
• CPU suspends until a programmable wakeup event.
suspend).
register [0xC098]) causing OTGVBUS to drop below 0.2V.
Otherwise OTGVBUS will only drop to V
diode drops).
CY7C67200
EZ-OTG
Code / Data
Int. 16k x8
nRESET
XOUT
XIN
* Parallel Resonant
Fundamental Mode
500uW
20-33pf ±5%
12MHz
Reset
Logic
22pf
22pf
CY7C67200
CC
– (2 schottky
Page 8 of 78
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