CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 56

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
Receive Bit Length (Bits [2:0])
The Receive Bit Length field controls whether a full byte or partial byte will be received. If Receive Bit Length is ‘000’ then a full
byte will be received. If Receive Bit Length is ‘001’ to ‘111’, then the value indicates the number of bits that will be received.
SPI Interrupt Enable Register [0xC0CC] [R/W]
Register Description
The SPI Interrupt Enable register controls the SPI port.
Receive Interrupt Enable (Bit 2)
The Receive Interrupt Enable bit enables or disables the byte
mode receive interrupt (RxIntVal).
1: Enable byte mode receive interrupt
0: Disable byte mode receive interrupt
Transmit Interrupt Enable (Bit 1)
The Transmit Interrupt Enable bit enables or disables the byte
mode transmit interrupt (TxIntVal).
SPI Status Register [0xC0CE] [R]
Register Description
The SPI Status register is a read only register that provides
status for the SPI port.
FIFO Error Flag (Bit 7)
The FIFO Error Flag bit is a read only bit that indicates if a FIFO
error occurred. When this bit is set to ‘1’ and the Transmit
Empty bit of the SPI Control register is set to ‘1’, then a Tx FIFO
underflow has occurred. Similarly, when set with the Receive
Full bit of the SPI Control register, a Rx FIFO overflow has
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
FIFO Error
Flag
7
0
-
15
15
R
0
0
7
0
-
-
6
0
-
14
14
6
0
0
0
-
-
-
...Reserved
Figure 63. SPI Interrupt Enable Register
5
0
-
Figure 64. SPI Status Register
13
13
5
0
0
0
-
-
-
Reserved
4
0
-
12
12
0
4
0
0
-
-
-
Reserved...
1: Enables byte mode transmit interrupt
0: Disables byte mode transmit interrupt
Transfer Interrupt Enable (Bit 0)
The Transfer Interrupt Enable bit enables or disables the block
mode interrupt (XfrBlkIntVal).
1: Enables block mode interrupt
0: Disables block mode interrupt
Reserved
All reserved bits must be written as ‘0’.
occured.This bit automatically clear when the SPI FIFO Init
Enable bit of the SPI Control register is set.
1: Indicates FIFO error
0: Indicates no FIFO error
Receive Interrupt Flag (Bit 2)
The Receive Interrupt Flag is a read only bit that indicates if a
byte mode receive interrupt has triggered.
1: Indicates a byte mode receive interrupt has triggered
0: Indicates a byte mode receive interrupt has not triggered
Reserved
3
0
-
11
11
0
3
0
0
-
-
-
Interrupt Enable
Receive
R/W
2
0
Interrupt Flag
Receive
10
10
R
0
2
0
0
-
-
Interrupt Enable
Transmit
Interrupt Flag
R/W
1
0
Transmit
R
1
0
9
0
9
0
-
-
CY7C67200
Interrupt Enable
Page 56 of 78
Interrupt Flag
Transfer
Transfer
R/W
0
0
R
0
0
8
0
8
0
-
-
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