CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 40

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
VBUS Valid Flag (Bit 0)
The VBUS Valid Flag bit indicates whether OTG VBus is
greater than 4.4V. After turning on VBUS, firmware should wait
at least 10 µs before this reading this bit.
GPIO Registers
There are seven registers dedicated for GPIO operations. These seven registers are covered in this section and summarized in
Table
Table 29.GPIO Registers
GPIO Control Register [0xC006] [R/W]
Register Description
The GPIO Control register configures the GPIO pins for
various interface options. It also controls the polarity of the
GPIO interrupt on IRQ0 (GPIO24).
Write Protect Enable (Bit 15)
The Write Protect Enable bit enables or disables the GPIO
write protect. When Write Protect is enabled, the GPIO Mode
Select [15:8] bits are read-only until a chip reset.
1: Enable Write Protect
0: Disable Write Protect
SAS Enable (Bit 11)
The SAS Enable bit, when in SPI mode, reroutes the SPI port
SPI_nSSI pin to GPIO[15] rather then GPIO[9].
1: Reroute SPI_nss to GPIO[15]
0: Leave SPI_nss on GPIO[9]
GPIO Control Register
GPIO0 Output Data Register
GPIO0 Input Data Register
GPIO0 Direction Register
GPIO1 Output Data Register
GPIO1 Input Data Register
GPIO1 Direction Register
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
29.
Write Protect
Enable
Enable
R/W
HSS
R/W
15
0
7
0
Register Name
Reserved
Reserved
14
0
6
0
-
-
Figure 41. GPIO Control Register
Enable
R/W
SPI
13
R
0
5
0
Reserved
12
0
4
0
-
-
1: OTG VBus is greater then 4.4V
0: OTG VBus is less then 4.4V
Reserved
All reserved bits must be written as ‘0’.
Mode Select (Bits [10:8])
The Mode Select field selects how GPIO[15:0] and
GPIO[24:19] are used as defined in
Table 30.Mode Select Definition
Mode Select
[10:8]
110
101
100
011
010
001
000
111
Reserved
Enable
SAS
R/W
11
0
3
0
-
Address
0xC01E
0xC006
0xC020
0xC022
0xC024
0xC026
0xC028
Reserved
SCAN – (HW) Scan diagnostic. For produc-
tion test only. Not for normal operation
HPI – Host Port Interface
Reserved
Reserved
Reserved
Reserved
GPIO – General Purpose Input Output
R/W
10
0
2
0
-
GPIO Configuration
Polarity Select
Interrupt 0
Table
Select
Mode
R/W
R/W
9
0
1
0
CY7C67200
30.
R/W
R/W
R/W
R/W
R/W
R/W
Page 40 of 78
R
R
Interrupt 0
Enable
R/W
R/W
8
0
0
0
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