CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet - Page 15

• Manufacturer Part Number: CY7C67200-48BAXI
• Description: USB HOST/PERIPH CNTRLR 48LFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-OTG™r
• Type: OTG Programmable USB On The Gor

Specifications of CY7C67200-48BAXI

• Package / Case: 48-LFBGA
• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 3.6 V, 3 V ~ 3.6 V
• Current - Supply: 80mA, 135mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Operating Supply Voltage: 2.7 V to 3.6 V
• Controller Family/series: PSoC 1
• Core Size: 16 Bit
• No. Of I/o's: 25
• Program Memory Size: 16KB
• Ram Memory Size: 8KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2262; CY7C67200-48BAXI

Document #: 38-08014 Rev. *G
UART Interrupt Enable (Bit 3)
The UART Interrupt Enable bit enables or disables the
following UART hardware interrupts: UART TX and UART RX.
1: Enable UART interrupt
0: Disable UART interrupt
GPIO Interrupt Enable (Bit 2)
The GPIO Interrupt Enable bit enables or disables the General
Purpose IO Pins Interrupt (See the GPIO Control Register).
When GPIO bit is reset, all pending GPIO interrupts are also
cleared.
1: Enable GPIO interrupt
0: Disable GPIO interrupt
Breakpoint Register [0xC014] [R/W]
Register Description
The Breakpoint Register holds the breakpoint address. When the program counter match this address, the INT127 interrupt
occurs. To clear this interrupt, a zero value must be written to this register.
Address (Bits [15:0])
The Address field is a 16-bit field containing the breakpoint address.
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
R/W
R/W
15
0
7
0
R/W
R/W
14
0
6
0
Figure 13. Breakpoint Register
R/W
R/W
13
0
5
0
R/W
R/W
12
0
4
0
Timer 1 Interrupt Enable (Bit 1)
The Timer 1 Interrupt Enable bit enables or disables the
TImer1 Interrupt Enable. When this bit is reset, all pending
Timer 1 interrupts are cleared.
1: Enable TM1 interrupt
0: Disable TM1 interrupt
Timer 0 Interrupt Enable (Bit 0)
The Timer 0 Interrupt Enable bit enables or disables the
TImer0 Interrupt Enable. When this bit is reset, all pending
Timer 0 interrupts are cleared.
1: Enable TM0 interrupt
0: Disable TM0 interrupt
Reserved
All reserved bits must be written as ‘0’.
Address...
...Address
R/W
R/W
11
0
3
0
R/W
R/W
10
0
2
0
R/W
R/W
9
0
1
0
CY7C67200
Page 15 of 78
R/W
R/W
8
0
0
0
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