TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 11
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Company
Part Number
Manufacturer
Quantity
Price
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8. Input/Output Ports
7.2 Reset Exceptions......................................................................................................................63
7.3 Non-Maskable Interrupts (NMI)..............................................................................................64
7.4 SysTick....................................................................................................................................64
7.5 Interrupts..................................................................................................................................65
7.6 Exception/Interrupt-Related Registers.....................................................................................74
8.1 Port Functions........................................................................................................................103
8.2 Port functions.........................................................................................................................108
7.5.1
7.5.2
7.6.1
7.6.2
7.6.3
8.1.1
8.1.2
8.1.3
8.1.4
8.2.1
8.2.2
7.1.2.1
7.1.2.2
7.1.2.3
7.1.2.4
7.5.1.1
7.5.1.2
7.5.1.3
7.5.1.4
7.5.1.5
7.5.1.6
7.5.2.1
7.5.2.2
7.5.2.3
7.5.2.4
7.5.2.5
7.5.2.6
7.6.2.1
7.6.2.2
7.6.2.3
7.6.2.4
7.6.2.5
7.6.2.6
7.6.2.7
7.6.2.8
7.6.2.9
7.6.2.10
7.6.2.11
7.6.2.12
7.6.2.13
7.6.2.14
7.6.2.15
7.6.2.16
7.6.2.17
7.6.3.1
7.6.3.2
7.6.3.3
7.6.3.4
7.6.3.5
7.6.3.6
7.6.3.7
8.2.1.1
8.2.1.2
8.2.1.3
8.2.1.4
8.2.1.5
8.2.1.6
8.2.1.7
8.2.1.8
Interrupt Sources................................................................................................................................................................65
Interrupt Handling..............................................................................................................................................................69
Register List.......................................................................................................................................................................74
NVIC Registers..................................................................................................................................................................75
Clock generator registers...................................................................................................................................................93
Function Lists..................................................................................................................................................................103
Port Registers Outline......................................................................................................................................................106
Port States in STOP Mode...............................................................................................................................................107
Precautions for Mode Transition between STOP and SLEEP.........................................................................................107
Port A (PA0 to PA7)........................................................................................................................................................108
Port B (PB0 to PB7).........................................................................................................................................................113
Exception Request and Detection
Exception Handling and Branch to the Interrupt Service Routine (Pre-emption)
Executing an ISR
Exception exit
Interrupt Route
Generation
Transmission
Precautions when using external interrupt pins
List of Interrupt Sources
Active level
Flowchart
Preparation
Detection by Clock Generator
Detection by CPU
CPU processing
Interrupt Service Routine (ISR)
SysTick Control and Status Register
SysTick Reload Value Register
SysTick Current Value Register
SysTick Calibration Value Register
Interrupt Set-Enable Register 1
Interrupt Set-Enable Register 2
Interrupt Clear-Enable Register 1
Interrupt Clear-Enable Register 2
Interrupt Set-Pending Register 1
CGIMCGA(CG Interrupt Mode Control Register A)
CGIMCGB(CG Interrupt Mode Control Register B)
CGIMCGC(CG Interrupt Mode Control Register C)
CGIMCGD(CG Interrupt Mode Control Register D)
CGICRCG(CG Interrupt Request Clear Register)
CGNMIFLG(NMI Flag Register)
CGRSTFLG (Reset Flag Register)
Port A Circuit Type
Port A register
PADATA (Port A data register)
PACR (Port A output control register)
PAFR1 (Port A function register 1)
PAPUP (Port A pull-up control register)
PAPDN (Port A pull-down control register)
PAIE (Port A input control register)
Interrupt Set-Pending Register 2
Interrupt Clear-Pending Register 1
Interrupt Clear-Pending Register 2
Interrupt Priority Register
Vector Table Offset Register
Application Interrupt and Reset Control Register
System Handler Priority Register
System Handler Control and State Register
iii
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