TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 352

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12.4
Operations
12.4.2.2
<CECHNC[1:0]> = 10 (3 samplings)
<CECLNC[2:0]> = 011 (4 samplings)
CEC line
Sampling
clock
After
sampling
After
noise cancellation
Register 1 <CECRCR1>, the Receive Control Register 2 <CECRCR2> and the Receive Control Register 3
<CECRCR3> are required.
(1)
(2)
Before receiving data, reception settings to the Logical Address Register <CECADD>, the Receive Control
Preconfiguration
be set simultaneously since every bit in this register corresponds with each address.
CECRCR1 register. It is considered as noise if "High"or "Low"of the same number as the specified
value are not sampled.You can configure the time to detect "High" and "Low" respectively.
A CEC line is monitored at each rising edge of a sampling clock. In the case that the CEC line is changed
from "High" to "Low", the change is fully recognized if "Low"s of the same number as specified in the
<CECLNC> bit are monitored. In the case that the CEC line is changed from "Low" to "High", the
change is fully recognized if "High" of the same number as specified in the <CECHNC> bit are sampled.
[1:0]> = "10" (3 samplings) and <CECLNC[2:0]> = "011" (4 samplings). By cancelling the noise, a
signal "1" shifts to "0" after "0" is sampled four times. The signal "0" shifts to "1" after "1" is sampled
three times.
Configure logical address assigned to this product to the CECADD register. Multiple addresses can
The noise cancellation time is configurable with the <CECHNC> and <CECLNC> bits of the
The following illustrates the operation of a case that a noise cancelling is configured as <CECHNC
Note:A broadcast message is received regardless of the CECADD register setting. By allocating a
Note:<CECLNC> must be used under the same setting as CECTCR<CECDTRS>.
Logical Address Configuration
Noise Cancellation Time
logical address of a device to 15, logical "0" is sent as an ACK response to the broadcast mes-
sage.
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TMPM330FDFG/FYFG/FWFG