TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 364

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12.4
Operations
12.4.3.5
12.4.3.6
pletion interrupt.
mission.
starting the transmission.
(2)
(3)
(4)
To stop transmission, send data including the EOM bit that indicates "1". This generates a transmit com-
Please note that proper operation is not ensured if the start bit of transmission is set to "0" during trans-
Transmission is stopped by error detection. To retry the transmission, configure the condition and data of
Stopping Transmission
Retransmission
in the CECTCR <CECBRD> bit.
mission of a byte of data, the transmit buffer underrun has priority.
An ACK error interrupt occurs when an ACK response does not conform to the configuration specified
When the ACK error interrupt occurs, the CECTSTAT <CECTIACK> bit is set.
The ACK error is detected in the following cases.
A transmit buffer underrun error is caused by the following sequence.
1. Data in the transmit buffer is transmit to the shift register.
2. An interrupt occurs.
3. A byte of data is transmitted.
4. No data is set to the transmit buffer before starting transmission of a byte of subsequent data.
When an underrun error occurs, the CECTSTAT <CECTIUR> bit is set.
If interrupt factors of the ACK error and transmit buffer underrun are detected at the end of trans-
The transmit buffer underrun interrupt occurs first and then the ACK error interrupt occurs.
ACK error
Transmit Buffer Underrun
Order of ACK Error and Transmit Buffer Overrun
Broadcast transmission?: Yes
Broadcast transmission?: No
<CECBRD> = 0
<CECBRD> = 1
Configuration
Page 344
ACK response is logical "1"
ACK response is logical "0"
Determined as an ACK error when
TMPM330FDFG/FYFG/FWFG