TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 374
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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13.3
Registers
13.3.8
31
30
29-26
25
24
23-16
15-8
7-0
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
RMCLIEN
RMCEDIEN
−
RMCLD
RMCPHM
−
RMCLL[7:0]
RMCDMAX[7:0]
RMCxRCR2(Receive Control Register 2)
Bit Symbol
RMCLIEN
31
23
15
0
0
1
7
1
-
R/W
R/W
R
R/W
R/W
R
R/W
R/W
Type
RMCEDIEN
30
22
14
0
0
1
6
1
-
Leader detection interrupt
0: Not generated
1: Generated
Remote control input falling edge interrupt
0: Not generated
1: Generated
Read as 0.
Receiving remote control signal with or without leader
0: Disabled
1: Enabled
Receiving a remote control signal by a phase modulation
0: Not receiving a remote control signal by a phase modulation. (receive by a cycle modulation)
1: Receive remote control signal by a fixed-frequency pulse modulation.
To receive a fixed-frequency remote control signal by a pulse modulation, set this bit to "1".
Read as 0.
Excess low width that triggers reception completion and interrupt generation.
0000_0000 to 1111_1110: Reception completion and interrupt generation at <RMCLL> × 1/fs [s].
1111_1111: not to use as the trigger
Maximum data bit cycle that triggers reception completion and interrupt generation.
0000_0000 to 1111_1110: Reception completion and interrupt generation at <RMCDMAX> × 1/fs [s].
1111_1111: not to use as the trigger
29
21
13
0
0
1
5
1
-
-
Page 354
28
20
12
0
0
1
4
1
-
-
RMCDMAX
RMCLL
27
19
11
0
0
1
3
1
-
-
Function
26
18
10
0
0
1
2
1
-
-
TMPM330FDFG/FYFG/FWFG
RMCLD
25
17
0
0
9
1
1
1
-
RMCPHM
24
16
0
0
8
1
0
1
-
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