TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 275
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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10.15
10.14.3
10.14.3.1
10.14.3.2
stete. Other states are maintained.
Software reset is generated by writing SCxMOD2<SWRST[1:0]> as "10" followed by "01".
As a result, SCxMOD0<RXE>, SCxMOD1<TXE>, SCxMOD2<TBEMP><RBFLL><TXRUN>, SCxCR
<OERR><PERR><FERR> are initialized. And the receive circuit, the transmit circuit and the FIFO become initial
Software Reset
Error Generation
Note:Over-run error and Under-run error have no meaning in SCLK output mode.
UART Mode
IO Interface Mode
Framing Error
Overrun Error
Parity Error
Overrun Error
Underrun Error
modes
Immediately after the raising / falling edge of the last SCLK
(Rising or falling is determined according to SCxCR<SCLKS> setting.)
Immediately after the rising or falling edge of the next SCLK.
(Rising or falling is determined according to SCxCR<SCLKS> setting.)
Page 255
9 bits
−
Around the center of stop bit
Around the center of parity bit
8 bits + Parity
7 bits+ Parity
7 bits
8 bits
TMPM330FDFG/FYFG/FWFG
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