TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 501
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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18.3.1
31-22
21-16
15-1
0
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
−
BLPRO5 to
BLPRO0
−
RDY/BSY
Note 1: This command must be issued in the ready state. Issuing the command in the busy state may disable both
Note 2: The value varies depending on protection applied.
Note 3: The FCFLCS[21:20] of TMPM330FWFG have no function. They are read as "0".
Bit Symbol
FCFLCS (Flash control register)
31
23
15
0
0
0
7
0
-
-
-
-
correct command transmission and further command input. To exit from the condition, execute system reset.
System reset requires at least 0.5 ms regardless of the system clock frequency. In this condition, it takes
approx. 2 ms to enable reading after reset.
R
R
R
R
Type
30
22
14
0
0
0
6
0
Read as 0.
Protection for Block5 to 0 (Note 3)
0: disabled
1: enabled
Protection status bits
Each of the protection bits represents the protection status of the corresponding block. When a bit is set to "1,"
it indicates that the block corresponding to the bit is protected. When the block is protected, data cannot be
written to it.
Read as 0.
Ready/Busy (Note 1)
0: Auto operating
1:Auto operation terminated
Ready/Busy flag bit
The RDY/BSY output is provided as a means to monitor the status of automatic operation. This bit is a function
bit for the CPU to monitor the function. When the flash memory is in automatic operation, it outputs "0" to indicate
that it is busy. When the automatic operation is terminated, it returns to the ready state and outputs "1" to accept
the next command. If the automatic operation has failed, this bit maintains the "0" output. By applying a hardware
reset, it returns to "1."
-
-
-
-
BLPRO5
(Note2)
29
21
13
0
0
5
0
-
-
-
Page 481
BLPRO4
(Note2)
28
20
12
0
0
4
0
-
-
-
BLPRO3
(Note2)
27
19
11
Function
0
0
3
0
-
-
-
BLPRO2
(Note2)
26
18
10
0
0
2
0
-
-
-
TMPM330FDFG/FYFG/FWFG
BLPRO1
(Note2)
25
17
0
9
0
1
0
-
-
-
RDY/BSY
BLPRO0
(Note2)
24
16
0
8
0
0
1
-
-
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