TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 487

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

17.3.1.3
17.3.1.4
termination during auto programming/ erasing or abnormal termination during automatic operation.
Therefore, when the RESET input pin of this device is set to VIL or when the CPU is reset due to any overflow
of the watch dog timer, the flash memory will return to the read mode terminating any automatic operation
that may be in progress. It should also be noted that applying a hardware reset during an automatic operation
can result in incorrect rewriting of data. In such a case, be sure to perform the rewriting again.
read the reset vector data from the flash memory and starts operation after the reset is removed.
(1)
A hardware reset is used to cancel the operational mode set by the command write operation when forcibly
The flash memory has a reset input as the memory block and it is connected to the CPU reset signal.
Refer to Section "17.2.1 Reset Operation" for CPU reset operations. After a given reset input, the CPU will
Reset(Hardware reset)
Commands
be changed to a "1" data cell. For making "0" data cells to "1" data cells, it is necessary to perform an
erase operation.
TMPM330FDFG/ TMPM330FYFG contain 128 words and the TMPM330FWFG contains 64 words
in a page. A 128 word block is defined by a same [31:9] address and it starts from the address [8:0] =
0x00 and ends at the address [8:0] = 0x1FF. A 64 word block is defined by a same [31:8] address and
it starts from the address [7:0] = 0x00 and ends at the address [7:0] = 0xFF. This programming unit is
hereafter referred to as a "page".
the CPU is required. The state of automatic page programming (whether it is in writing operation or
not) can be checked by FCFLCS [0] <RDY/BSY> .
mode. If it is desired to interrupt the automatic page programming, use the hardware reset function. If
the operation is stopped by a hardware reset operation, it is necessary to once erase the page and then
perform the automatic page programming again because writing to the page has not been normally
terminated.
gramming can be performed twice or more times irrespective of the data cell value whether it is "1" or
"0." Note that rewriting to a page that has been once written requires execution of the automatic block
erase or automatic chip erase command before executing the automatic page programming command
again. Note that an attempt to rewrite a page two or more times without erasing the content can cause
damages to the device.
programmed to confirm that it has been correctly written.
cycle is completed. On and after the fifth bus write cycle, data will be written sequentially starting from
Note 3: For the command sequencer to recognize a command, the device must be in the read mode
Note 4: Upon issuing a command, if any address or data is incorrectly written, be sure to perform
Writing to a flash memory device is to make "1" data cells to "0" data cells. Any "0" data cell cannot
The automatic page programming function of this device writes data of each page. The
Writing to data cells is automatically performed by an internal sequencer and no external control by
Also, any new command sequence is not accepted while it is in the automatic page programming
The automatic page programming operation is allowed only once for a page already erased. No pro-
No automatic verify operation is performed internally to the device. So, be sure to read the data
The automatic page programming operation starts when the third bus write cycle of the command
Automatic Page Programming
prior to executing the command. Be sure to check before the first bus write cycle that
FCFLCS <RDY/BSY> is set to "1." It is recommended to subsequently execute a Read com-
mand.
a software reset to return to the read mode again.
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TMPM330FDFG/FYFG/FWFG