TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 331

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12. Consumer Electronics Control (CEC)
12.1
Logical address match
Logical address disacre-
pancy
Address condition
12.1.1
12.1.2
12.1.3
CEC) protocol.
This IP enables to transmit or receive data that conforms to Consumer Electronics Control (hereafter referred to as
This IP can operate conformably to HDMI 1.3a specifications.
Outline
Be careful about the following in the receive operation.
Reception
Transmission
Precautions
・ Clock sampling at 32.768kHz
・ Data reception per 1byte
・ Error detection
・ Data transmission per 1byte
・ Flexible waveform
・ Error detection
−
When data reception at logical address
discrepancy is enabled.
(CECRCR1<CECOTH> = "1")
When data reception at logical address
discrepancy is disabled.
(CECRCR1<CECOTH> = "0")
Setting of CECRCR1<CECOTH>
-Adjustable noise canceling time
-Flexible data sampling point
-Data reception is available even when an address discrepancy is detected.
-Cycle error (min./max.)
-ACK collision
-Waveform error
-Triggered by auto-detection of bus free state
-Adjustable rising edge and cycle
-Arbitration lost
-ACK response error
If the initiator sends a new message beginning with the start bit without having sent the last
block with EOM="1", a maximum cycle error is determined for the ACK bit and an interrupt
is generated. Then, the receive operation is performed in the usual way.
The initiator must send the last block of data with the EOM bit set to "1". If the last block is
sent with EOM="0", the subsequent operation cannot be guaranteed.
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Precautions
TMPM330FDFG/FYFG/FWFG