TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 66
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
Quantity
Price
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6.3
Clock control
6.3.6
6.3.7
6.3.6.1
6.3.6.2
Table 6-2 Range of High Speed frequency
Input freq.
10MHz
X1, X2
8MHz
speed clock is dividable.
the "fperiph" clock specified in the CGSYSCR<FPSEL> can be divided according to the setting in the
CGSYSCR<PRCK[2:0]>. After the controller is reset, fperiph/1 is selected as φT0.
System Clock
Prescaler Clock Control
Note 1: Switching of clock gear is executed when a value is written to the CGSYSCR<GEAR[2:0]> register.
Note 2: The CEC function uses the low-speed clock as a sampling clock. The allowable margin of error when the
The TMPM330FDFG/FYFG/FWFG offers two selectable system clocks: low-speed or high-speed. The high-
Each peripheral function has a prescaler for dividing a clock. As the clock φT0 to be input to each prescaler,
Note:To use the clock gear, ensure that you make the time setting such that prescaler output φTn from
Input frequency from XT1 and XT2
High speed clock
Low speed clock
Note:PLL=ON/OFF setting: available in CGOSCCR<PLLON> Clock gear setting: available in
Min. oper-
ating freq.
1 MHz
The actual switching takes place after a slight delay.
CEC function is used is approximately ±4% at 32.768 kHz.
each peripheral function is slower than fsys (φTn < fsys). Do not switch the clock gear while the
timer counter or other peripheral function is operating.
・ Input frequency from X1 and X2: 8MHz to 10MHz
・ Allows for oscillator connection or external clock input
・ Clock gear:1/1, 1/2, 1/4, 1/8 (after reset: 1/1)
CGSYSCR<GEAR[2:0]>.
Max oper-
ating freq.
40 MHz
Table 6-3 Range of Low Speed Frequency
Input Frequency
30 to 34 (kHz)
Range
(PLL = OFF,
After reset
CG = 1/1)
10
8
Maximum Operating
1/1
32
40
Clock gear (CG) PLL = @ON
Page 46
Frequency
34 kHz
1/2
16
20
1/4
10
Minimum Operating
8
Frequency
30 kHz
1/8
4
5
1/1
10
8
Clock gear (CG) PLL = @OFF
TMPM330FDFG/FYFG/FWFG
1/2
4
5
1/4
2.5
2
1.25
1/8
1
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