TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 302

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11.5
Control in the I2C Bus Mode
11.5
11.5.1
11.5.1.1
11.5.1.2
Control in the I2C Bus Mode
Serial Clock
in the master mode.
pulls its clock line to the "Low" level overrides other masters producing the "High" level on their clock lines.
This must be detected and responded by the masters producing the "High" level.
"Low" level. Master B detects this transition, resets its "High" level period counter, and pulls its internal SCL
output level to the "Low" level.
SBIxCR1<SCK[2:0]> specifies the maximum frequency of the serial clock to be output from the SCL pin
The I2C bus is driven by using the wired-AND connection due to its pin structure. The first master that
Clock synchronization assures correct data transfer on a bus that has two or more master.
For example, the clock synchronization procedure for a bus with two masters is shown below.
At the point a, Master A pulls its internal SCL output to the "Low" level, bringing the SCL bus line to the
Note:The maximum speeds in the standard and high-speed modes are specified to 100kHz and
Internal SCL output
Internal SCL output
SCL line
Clock source
Clock Synchronization
400kHz respectively following the communications standards. Notice that the internal SCL clock
frequency is determined by the fsys used and the calculation formula shown above.
(Master A)
(Master B)
Figure 11-4 Example of Clock Synchronization
t
t
fscl = 1/(t
LOW
HIGH
=
= 2
= 2
2
n
fsys
n-1
n-1
LOW
+ 72
/fsys + 58/fsys
/fsys + 14/fsys
t
HIGH
+ t
Figure 11-3 Clock source
HIGH
a
Reset “High”level
period counting
)
t
LOW
Page 282
b
Wait for “High”level
period counting
SBIxCR1<SCK[2:0]>
c
1/fscl
000
001
010
011
100
101
110
Start “High” level period counting
10
11
n
5
6
7
8
9
TMPM330FDFG/FYFG/FWFG