TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 133

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TMPM330FWFG

Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Datasheets

Specifications of TMPM330FWFG

Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM330FWFG
Manufacturer:
Toshiba
Quantity:
10 000
8.2.2
Type
8.2.2.1
8.2.2.2
units of bits. Besides the general-purpose input/output function, the port B performs the debug interface.
enabled. PB1 is initialized as the TDI pin with input and pull-up enabled. PB2 is initialized as the TRST pin with
input and pull-up enabled.PB3 to PB7 are initialized as general-purpose ports with input, output and pull-up
disabled.
Port B data register
Port B output control register
Port B function register 1
Port B pull-up control register
Port B input control register
Port B (PB0 to PB7)
The port B is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in
Reset configures PB0, PB1 and PB2 as debug interface.PB0 is initialized as the TDO/SWV pin with output
Note:If PB0 is configured as the TDO/SWV pin, output is enabled even in STOP mode regardless of the
Port B Circuit Type
Port B Register
CGSTBYCR<DRVE> bit setting.
T1
7
T1
6
Register name
T1
5
Page 113
T1
4
PBDATA
PBPUP
PBFR1
PBCR
PBIE
T1
3
T2
2
Base Address = 0x4000_0040
TMPM330FDFG/FYFG/FWFG
Address (Base+)
0x002C
0x0000
0x0004
0x0008
0x0038
T2
1
T11
0

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