LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 10

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

List of Registers
List of Registers
System Control ............................................................................................................................... 48
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Internal Memory .............................................................................................................................. 86
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
General-Purpose Input/Outputs (GPIOs) .................................................................................... 100
Register 1:
Register 2:
10
Device Identification 0 (DID0), offset 0x000 .............................................................................. 56
Device Identification 1 (DID1), offset 0x004 .............................................................................. 57
Device Capabilities 0 (DC0), offset 0x008................................................................................. 59
Device Capabilities 1 (DC1), offset 0x010................................................................................. 60
Device Capabilities 2 (DC2), offset 0x014................................................................................. 62
Device Capabilities 3 (DC3), offset 0x018................................................................................. 63
Device Capabilities 4 (DC4), offset 0x01C ................................................................................ 64
Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................ 65
LDO Power Control (LDOPCTL), offset 0x034.......................................................................... 66
Software Reset Control 0 (SRCR0), offset 0x040 ..................................................................... 67
Software Reset Control 1 (SRCR1), offset 0x044 ..................................................................... 68
Software Reset Control 2 (SRCR2), offset 0x048 ..................................................................... 69
Raw Interrupt Status (RIS), offset 0x050................................................................................... 70
Interrupt Mask Control (IMC), offset 0x054 ............................................................................... 71
Masked Interrupt Status and Clear (MISC), offset 0x058.......................................................... 73
Reset Cause (RESC), offset 0x05C .......................................................................................... 74
Run-Mode Clock Configuration (RCC), offset 0x060................................................................. 75
XTAL to PLL Translation (PLLCFG), offset 0x064 .................................................................... 79
Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100 ....................................................... 80
Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110..................................................... 80
Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120........................................... 80
Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104 ....................................................... 81
Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114..................................................... 81
Deep-Sleep-Mode Clock Gating Control 1 (DCGC1), offset 0x124........................................... 81
Run-Mode Clock Gating Control 2 (RCGC2), offset 0x108 ....................................................... 83
Sleep-Mode Clock Gating Control 2 (SCGC2), offset 0x118..................................................... 83
Deep-Sleep-Mode Clock Gating Control 2 (DCGC2), offset 0x128........................................... 83
Clock Verification Clear (CLKVCLR), offset 0x150.................................................................... 84
Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 ....................................... 85
Flash Memory Protection Read Enable (FMPRE), offset 0x130 ............................................... 91
Flash Memory Protection Program Enable (FMPPE), offset 0x134 .......................................... 91
USec Reload (USECRL), offset 0x140...................................................................................... 92
Flash Memory Address (FMA), offset 0x000 ............................................................................. 93
Flash Memory Data (FMD), offset 0x004 .................................................................................. 94
Flash Memory Control (FMC), offset 0x008 .............................................................................. 95
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ................................................... 97
Flash Controller Interrupt Mask (FCIM), offset 0x010 ............................................................... 98
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014........................... 99
GPIO Data (GPIODATA), offset 0x000 ................................................................................... 108
GPIO Direction (GPIODIR), offset 0x400 ................................................................................ 109
Preliminary
July 6, 2006