LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 307

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

16
Table 16-1. Signals by Pin Number (Sheet 1 of 2)
July 6, 2006
Number
Pin
10
12
13
11
1
2
3
4
5
6
7
8
9
Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register (see page 117).
Important:
Table 16-1 shows the pin-to-signal-name mapping, including functional characteristics of the
signals. Table 16-2 lists the signals in alphabetical order by signal name. Table 16-3 groups the
signals by functionality, except for GPIOs. Table 16-4 lists the GPIO pins and their alternate
functionality.
Signal Name
PB7
TRST
PB6
CCP1
C0+
PB5
C0o
PB4
C0–
RST
LDO
VDD
GND
OSC0
OSC1
PA0
U0Rx
PA1
U0Tx
PA2
SSIClk
All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins
(PB7 and PC[3:0]) which default to the JTAG functionality.
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
-
-
-
I
I
Analog
Analog
Analog
Analog
Buffer
Power
Power
Power
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Preliminary
Description
GPIO port B bit 7.
JTAG TAP reset input.
GPIO port B bit 6.
Timer 0 capture input, compare output, or PWM output port 1.
Analog comparator 0 positive reference input.
GPIO port B bit 5.
Analog comparator 0 output.
GPIO port B bit 4.
Analog comparator 0 negative reference input.
System reset input.
The linear drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 μF or greater.
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Oscillator crystal input or an external clock reference input.
Oscillator crystal output.
GPIO port A bit 0.
UART0 receive data input.
GPIO port A bit 1.
UART0 transmit data output.
GPIO port A bit 2.
master mode).
SSI clock reference (input when in slave mode and output in
LM3S102 Data Sheet
307