LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 25

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

1.4.4
1.4.4.1
1.4.4.2
1.4.4.3
July 6, 2006
The LM3S102 controller provides one analog comparator that can be configured to drive an output
or generate an interrupt.
A comparator can compare a test voltage against any one of these voltages:
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts to cause it to
start capturing a sample sequence. The interrupt generation logic is separate.
Serial Communications Peripherals
The LM3S102 controller supports both asynchronous and synchronous serial communications
with one fully programmable 16C550-type UART, SSI and I
UART (Section 11 on page 193)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S102 controller includes one fully programmable 16C550-type UART that supports data
transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not
register compatible.)
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are
asserted and are unmasked.
SSI (Section 12 on page 229)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The Stellaris SSI module provides the functionality for synchronous serial communications with
peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE, or TI
synchronous serial interface frame formats. The size of the data frame is also configurable, and
can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module’s input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
I
The Inter-Integrated Circuit (I
design (a serial data line SDA and a serial clock line SCL).
2
C (Section 13 on page 263)
An individual external reference voltage
A shared single external reference voltage
A shared internal reference voltage
2
C) bus provides bi-directional data transfer through a two-wire
Preliminary
2
C serial communications.
LM3S102 Data Sheet
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