LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 13

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Register 23:
Register 24:
Synchronous Serial Interface (SSI) ............................................................................................. 229
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 263
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Analog Comparator ...................................................................................................................... 295
Register 1:
Register 2:
Register 3:
Register 4:
July 6, 2006
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8............................................. 227
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ............................................ 228
SSI Control 0 (SSICR0), offset 0x000 ..................................................................................... 240
SSI Control 1 (SSICR1), offset 0x004 ..................................................................................... 242
SSI Data (SSIDR), offset 0x008 .............................................................................................. 244
SSI Status (SSISR), offset 0x00C ........................................................................................... 245
SSI Clock Prescale (SSICPSR), offset 0x010 ......................................................................... 246
SSI Interrupt Mask (SSIIM), offset 0x014 ................................................................................ 247
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .................................................................... 248
SSI Masked Interrupt Status (SSIMIS), offset 0x01C.............................................................. 249
SSI Interrupt Clear (SSIICR), offset 0x020.............................................................................. 250
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0.................................................. 251
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4.................................................. 252
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8.................................................. 253
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ................................................. 254
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0.................................................. 255
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4.................................................. 256
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8.................................................. 257
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ................................................. 258
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0..................................................... 259
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4..................................................... 260
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8..................................................... 261
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC .................................................... 262
I2C Master Slave Address (I2CMSA), offset 0x000 ................................................................ 274
I2C Master Control/Status (I2CMCS), offset 0x004................................................................. 275
I2C Master Data (I2CMDR), offset 0x008................................................................................ 280
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00........................................ 299
Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04.............................................. 300
Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ................................................ 301
Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ............................ 302
2
2
2
2
2
2
2
2
2
2
2
2
2
C Master Timer Period (I2CMTPR), offset 0x00C ................................................................ 281
C Master Interrupt Mask (I2CMIMR), offset 0x010 ............................................................... 282
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ...................................................... 283
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ................................................ 284
C Master Interrupt Clear (I2CMICR), offset 0x01C ............................................................... 285
C Master Configuration (I2CMCR), offset 0x020 .................................................................. 286
C Slave Own Address (I2CSOAR), offset 0x000 .................................................................. 287
C Slave Control/Status (I2CSCSR), offset 0x004 ................................................................. 288
C Slave Data (I2CSDR), offset 0x008................................................................................... 290
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ................................................................. 291
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010......................................................... 292
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014................................................... 293
C Slave Interrupt Clear (I2CSICR), offset 0x018 .................................................................. 294
Preliminary
LM3S102 Data Sheet
13