LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 61
LM3S102
Manufacturer Part Number
LM3S102
Description
Lm3s102 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S102.pdf
(330 pages)
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a. These bits mask the Run-Mode Clock Gating Control 0 (RCGC0) register (see page 113), Sleep-Mode Clock Gating Control 0
July 6, 2006
(SCGC0) register (see page 113), and Deep-Sleep-Mode Clock Gating Control 0 (DCGC0) register (see page 113). Bits that are
not noted are passed as 0.
Bit/Field
1
0
JTAG
SWD
Name
a
a
Type
RO
RO
Reset
Preliminary
1
1
Description
A 1 in this bit indicates the presence of the ARM Serial Wire
Debug (SWD) capabilities.
A 1 in this bit indicates the presence of a JTAG port.
LM3S102 Data Sheet
61
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