LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 264

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Inter-Integrated Circuit (I2C) Interface
13.2.1
13.2.1.1
13.2.1.2
13.2.1.3
264
Figure 13-2. I
I
The I
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line.
Data Transfers
Both the SDA and SCL lines are bi-directional, connected to the positive supply via pull-up
resistors. The bus is idle or free, when both lines are High. The output devices (pad drivers) must
have an open-drain configuration. Data on the I
in Standard mode and up to 400 Kbps in Fast mode.
Data Validity
The data on the SDA line must be stable during the High period of the clock. The data line can only
change when the clock SCL is in its Low state (see Figure 13-3).
Figure 13-3. Data Validity During Bit Transfer on the I
START and STOP Conditions
The protocol of the I
SDA line while the SCL is High is a START condition. A Low-to-High transition on the SDA line
while SCL is High is defined as a STOP condition. The bus is considered busy after a START
condition. The bus is considered free after a STOP condition. See Figure 13-4.
Figure 13-4. START and STOP Conditions
2
C Bus Functional Overview
2
C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris
SDA
SCL
2
C Bus Configuration
condition
START
SDA
SCL
2
C bus defines two states: START and STOP. A High-to-Low transition on the
SDA
SCL
I2CSCL I2CSDA
Stellaris TM
Preliminary
Data line
R PUP
stable
with I 2 C Interface
3rd Party Device
SCL
R PUP
allowed
2
Chan ge
of data
C bus can be transferred at rates up to 100 Kbps
SDA
with I 2 C Interface
2
3rd Party Device
C Bus
SCL
SDA
condition
I 2 C Bus
STOP
SDA
SCL
July 6, 2006