LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 249

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

July 6, 2006
Reset
Reset
Type
Type
SSI Masked Interrupt Status (SSIMIS)
Offset 0x01C
Bit/Field
RO
RO
31
15
0
0
31:4
3
2
1
0
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
RO
RO
30
14
0
0
reserved
RORMIS
RXMIS
TXMIS
RTMIS
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
RO
RO
27
11
0
0
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
reserved
Reset
RO
RO
25
0
0
0
0
0
0
9
0
Preliminary
RO
RO
24
0
8
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
Indicates that the transmit FIFO is half empty or more, when
set.
SSI Receive FIFO Masked Interrupt Status
Indicates that the receive FIFO is half empty or more, when
set.
SSI Receive Time-Out Masked Interrupt Status
Indicates that the receive time-out has occurred, when set.
SSI Receive Overrun Masked Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
SSI Transmit FIFO Masked Interrupt Status
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
TXMIS
RO
RO
19
0
3
0
RXMIS
LM3S102 Data Sheet
RO
RO
18
0
2
0
RTMIS
RO
RO
17
0
1
0
RORMIS
RO
RO
16
0
0
0
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