LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 140

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

General-Purpose Timers
9.2.2
9.2.2.1
9.2.2.2
140
32-Bit Timer Operating Modes
Note:
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and
their configuration.
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain
GPTM registers are concatenated to form pseudo 32-bit registers. These registers include:
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
value:
32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB
registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is
determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR)
register (see page 151), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR)
register.
When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 153), the
timer begins counting down from its preloaded value. Once the 0x00000000 state is reached, the
timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to
be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If
configured as a periodic timer, it continues counting.
In addition to reloading the count value, the GPTM generates interrupts and output triggers when it
reaches the 0x0000000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt
Status (GPTMRIS) register (see page 157), and holds it until it is cleared by writing the GPTM
Interrupt Clear (GPTMICR) register (see page 159). If the time-out interrupt is enabled in the
GPTM Interrupt Mask (GPTIMR) register (see page 155), the GPTM also sets the TATOMIS bit in
the GPTM Masked Interrupt Status (GPTMISR) register (see page 158).
The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the
0x00000000 state, and deasserted on the following clock cycle. It is enabled by setting the TAOTE
bit in GPTMCTL.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the
new value on the next clock cycle and continues counting from the new value.
If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal
is deasserted.
32-Bit Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is
loaded with a value of 0x00000001. All subsequent load values must be written to the GPTM
TimerA Match (GPTMTAMATCHR) register (see page 162) by the controller.
GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 160
GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 161
GPTM TimerA (GPTMTAR) register [15:0], see page 168
GPTM TimerB (GPTMTBR) register [15:0], see page 169
GPTMTBR[15:0]:GPTMTAR[15:0]
The odd-numbered CCP pins are used for 16-bit input and the even-numbered CCP pins
are used for 32-bit input.
Preliminary
. Likewise, a read access to GPTMTAR returns the
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July 6, 2006