LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 276

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Inter-Integrated Circuit (I2C) Interface
276
Write-Only Control Register
Bit/Field
31:7
6-4
4
3
2
1
0
3
2
1
0
ADRACK
DATACK
ARBLST
reserved
reserved
ERROR
START
BUSY
Name
STOP
RUN
ACK
Type
RO
W
W
W
W
W
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
0
0
0
Preliminary
Description
This bit specifies the result of bus arbitration. If set, the controller
lost arbitration; otherwise, the controller won arbitration.
This bit specifies the result of the last data operation. If set, the
transmitted data was not acknowledged; otherwise, the data
was acknowledged.
the transmitted address was not acknowledged; otherwise, the
address was acknowledged.
This bit specifies the result of the last bus operation. If set, an
error occurred on the last operation; otherwise, no error was
detected. The error can be from the slave address not being
acknowledged, the transmit data not being acknowledged, or
because the controller lost arbitration.
This bit specifies the state of the controller. If set, the controller
is busy; otherwise, the controller is idle. When the BUSY bit is
set, the other status bits are not valid.
Reserved bits return an indeterminate value, and should never
be changed.
Write reserved.
When set, causes received data byte to be acknowledged
automatically by the master. See field decoding in Table 13-3 on
page 277.
When set, causes the generation of the STOP condition. See
field decoding in Table 13-3.
When set, causes the generation of a START or repeated
START condition. See field decoding in Table 13-3.
When set, allows the master to send or receive data. See field
decoding in Table 13-3.
This bit specifies the result of the last address operation. If set,
July 6, 2006