LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 80

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

System Control
80
Reset
Reset
Type
Type
31:2016
Bit/Field
Run-Mode, Sleep-Mode and Deep-Sleep-Mode Clock Gating Control 0 (RCGC0, SCGC0, and DCGC0)
Offset 0x100, 0x110, 0x120
3
2
1
0
:
RO
RO
31
15
0
0
Register 19: Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100
Register 20: Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110
Register 21: Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120
These registers control the clock gating logic. Each bit controls a clock enable for a given
interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled (saving power). The reset state of these bits is 0 (unclocked) unless
otherwise noted, so that all functional units are disabled. It is the responsibility of software to
enable the ports necessary for the application. Note that these registers may contain more bits
than there are interfaces, functions, or units to control. This is to assure reasonable code
compatibility with other family and future parts.
RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and
DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration
(RCC) register (see page 75) specifies that the system uses sleep modes.
RO
RO
30
14
0
0
reserved
reserved
Name
JTAG
SWO
SWD
WDT
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
R/W
R/W
R/W
RO
RO
RO
RO
26
10
0
0
reserved
RO
RO
Reset
25
0
9
0
Preliminary
0
0
0
0
0
1
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
Reserved bits return an indeterminate value, and should
never be changed.
This bit controls the clock gating for the WDT module. If set,
the unit receives a clock and functions. Otherwise, the unit
is unclocked and disabled.
This bit controls the clock gating for the SWO module. If
set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled.
This bit controls the clock gating for the SWD module. If set,
the unit receives a clock and functions. Otherwise, the unit
is unclocked and disabled.
This bit controls the clock gating for the JTAG module. The
reset state for this bit is 1. At reset, the unit receives a clock
and functions. Setting this bit to 0 leaves the unit unclocked
and disabled.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
WDT
R/W
RO
19
0
3
0
SWO
R/W
RO
18
0
2
0
SWD
R/W
RO
17
July 6, 2006
0
1
0
JTAG
R/W
RO
16
0
0
1