LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 12

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

List of Registers
Register 17:
Register 18:
Watchdog Timer............................................................................................................................ 170
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Universal Asynchronous Receiver/Transmitter (UART) ........................................................... 193
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
12
GPTM TimerA (GPTMTAR), offset 0x048 ............................................................................... 168
GPTM TimerB (GPTMTBR), offset 0x04C .............................................................................. 169
Watchdog Load (WDTLOAD), offset 0x000 ............................................................................ 173
Watchdog Value (WDTVALUE), offset 0x004 ......................................................................... 174
Watchdog Control (WDTCTL), offset 0x008............................................................................ 175
Watchdog Interrupt Clear (WDTICR), offset 0x00C ................................................................ 176
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ....................................................... 177
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014.................................................. 178
Watchdog Lock (WDTLOCK), offset 0xC00 ............................................................................ 179
Watchdog Test (WDTTEST), offset 0x418 .............................................................................. 180
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0..................................... 181
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4..................................... 182
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8..................................... 183
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC .................................... 184
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ..................................... 185
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ..................................... 186
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ..................................... 187
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC .................................... 188
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0........................................ 189
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4........................................ 190
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8........................................ 191
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ...................................... 192
UART Data (UARTDR), offset 0x000 ...................................................................................... 200
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 .............................. 202
UART Flag (UARTFR), offset 0x018 ....................................................................................... 204
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ................................................. 206
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ........................................... 207
UART Line Control (UARTLCRH), offset 0x02C ..................................................................... 208
UART Control (UARTCTL), offset 0x030................................................................................. 210
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ................................................ 211
UART Interrupt Mask (UARTIM), offset 0x038 ........................................................................ 212
UART Raw Interrupt Status (UARTRIS), offset 0x03C............................................................ 214
UART Masked Interrupt Status (UARTMIS), offset 0x040 ...................................................... 215
UART Interrupt Clear (UARTICR), offset 0x044...................................................................... 216
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0.......................................... 217
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4.......................................... 218
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8.......................................... 219
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ......................................... 220
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0.......................................... 221
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4.......................................... 222
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8.......................................... 223
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ......................................... 224
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0............................................. 225
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4............................................. 226
Preliminary
July 6, 2006