LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 178

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Watchdog Timer
178
Reset
Type
Reset
Type
Bit/Field
Watchdog Masked Interrupt Status (WDTMIS)
Offset 0x014
31:1
RO
RO
31
15
0
0
0
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.
RO
RO
30
14
0
0
WDTMIS
reserved
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
Preliminary
reserved
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
Watchdog Masked Interrupt Status
Gives the masked interrupt state (after masking) of the
WDTINTR interrupt.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
RO
RO
17
July 6, 2006
0
1
0
WDTMIS
RO
RO
16
0
0
0