LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 99

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

July 6, 2006
Reset
Reset
Type
Type
Bit/Field
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Offset 0x014
RO
RO
31
15
0
0
31:2
1
0
Register 9: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear
the interrupt reporting.
RO
RO
30
14
0
0
reserved
PMISC
AMISC
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
R/W1C
R/W1C
Type
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
0
Preliminary
reserved
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
Programming Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled
because a programming cycle completed and was not
masked. This bit is cleared by writing a 1. The PRIS bit in
the FCRIS register (see page 97) is also cleared when the
PMISC bit is cleared.
Access Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled
because an improper access was attempted and was not
masked. This bit is cleared by writing a 1. The ARIS bit in
the FCRIS register is also cleared when the AMISC bit is
cleared.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
LM3S102 Data Sheet
RO
RO
18
0
2
0
PMISC
R/W1C
RO
17
0
1
0
AMISC
R/W1C
RO
16
0
0
0
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