LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 274

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LM3S102

Manufacturer Part Number
LM3S102
Description
Lm3s102 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet

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Inter-Integrated Circuit (I2C) Interface
274
Reset
Reset
Type
Type
Bit/Field
I2C Master Slave Address (I2CMSA)
Offset 0x000
RO
RO
31
15
0
0
31:8
7:1
0
Register 1: I
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Send (Low).
RO
RO
30
14
0
0
reserved
Name
R/S
SA
RO
RO
29
13
0
0
2
RO
RO
C Master Slave Address (I2CMSA), offset 0x000
28
12
0
0
reserved
Type
R/W
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
I
This field specifies bits A6 through A0 of the slave address.
Receive/Send
The R/S bit specifies if the next operation is a Receive (High) or
Send (Low).
0: Send
1: Receive
2
C Slave Address
RO
RO
24
0
8
0
reserved
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
SA
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
R/W
RO
17
July 6, 2006
0
1
0
R/S
R/W
RO
16
0
0
0

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