LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 275

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

July 6, 2006
Reset
Reset
Reset
Reset
Type
Type
Type
Type
Read-Only Status Register
Bit/Field
I2C Master Status (I2CMCS): Read
Offset 0x004
I2C Master Control (I2CMCS): Write
Offset 0x004
RO
RO
RO
RO
31
15
31
15
0
0
0
0
31:7
6
5
Register 2: I
This register accesses four control bits when written, and accesses seven status bits when read.
The status register consists of seven bits, which when read determine the state of the I
controller.
The control register consists of four bits: the RUN, START, STOP, and ACK bits.
The START bit causes the generation of the START, or REPEATED START condition.
The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst.
To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with
the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1),
STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is
completed (or aborted due an error), the interrupt pin becomes active and the data may be read
from the I2CMDR register. When the I
must be set normally to logic 1. This causes the I
automatically after each byte. This bit must be reset when the I
data to be sent from the slave transmitter.
RO
RO
RO
RO
30
14
30
14
0
0
0
0
BUSBSY
reserved
Name
IDLE
RO
RO
RO
RO
29
13
29
13
0
0
0
0
2
C Master Control/Status (I2CMCS), offset 0x004
RO
RO
RO
RO
28
12
28
12
0
0
0
0
Type
RO
R
R
RO
RO
RO
RO
27
27
0
11
0
0
11
0
RO
RO
RO
RO
26
10
26
10
0
0
0
0
reserved
reserved
Reset
0
0
0
RO
RO
RO
RO
25
25
0
9
0
0
9
0
Preliminary
2
Description
Reserved bits return an indeterminate value, and should never
be changed.
This bit specifies the state of the I
otherwise, the bus is idle. The bit changes based on the START
and STOP conditions.
This bit specifies the I
idle; otherwise the controller is not idle.
C module operates in Master receiver mode, the ACK bit
RO
RO
RO
RO
24
24
0
8
0
0
8
0
reserved
reserved
RO
RO
RO
RO
23
23
0
7
0
0
7
0
2
C bus controller to send an acknowledge
BUSBSY
RO
RO
RO
RO
22
22
0
0
0
6
0
6
2
IDLE
C controller state. If set, the controller is
RO
RO
RO
RO
21
21
0
0
0
5
0
5
2
C bus controller requires no further
ARBLST DATACK ADRACK ERROR
RO
RO
RO
20
20
RO
0
0
0
4
0
4
2
C bus. If set, the bus is busy;
ACK
WO
RO
RO
RO
19
19
0
3
0
0
3
0
LM3S102 Data Sheet
STOP
WO
RO
RO
RO
18
18
0
2
0
0
2
0
START
WO
RO
RO
RO
2
17
17
0
1
0
0
1
0
C bus
BUSY
RUN
WO
RO
RO
RO
16
16
0
0
0
0
0
0
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