LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 27

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

1.4.6
1.4.6.1
1.4.6.2
1.4.7
1.4.7.1
1.4.7.2
July 6, 2006
Memory Peripherals
The Stellaris controllers offer both SRAM and Flash memory.
SRAM (Section 7.2.1 on page 86)
The LM3S102 static random access memory (SRAM) controller supports 2 KB SRAM. The
internal SRAM of the Stellaris devices is located at address 0x20000000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has
introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled
processor, certain regions in the memory map (SRAM and peripheral space) can use address
aliases to access individual bits in a single, atomic operation.
Flash (Section 7.2.2 on page 87)
The LM3S102 Flash controller supports 8 KB of flash memory. The flash is organized as a set of
1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of
code protection. Read-only blocks cannot be erased or programmed, protecting the contents of
those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can
only be read by the controller instruction fetch mechanism, protecting the contents of those blocks
from being read by either the controller or by a debugger.
Additional Features
Memory Map (Section 3 on page 33)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S102 controller can be found on page 33. Register addresses are given as a hexadecimal
increment, relative to the module’s base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
JTAG TAP Controller (Section 5 on page 38)
The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the
Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG
data registers can be used to test the interconnects of assembled printed circuit boards, obtain
manufacturing information on the components, and observe and/or control the inputs and outputs
of the controller during normal operation. The JTAG port provides a high degree of testability and
chip-level access at a low cost.
The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The LMI JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is
implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions
select the ARM TDO output while LMI JTAG instructions select the LMI TDO outputs. The
multiplexer is controlled by the LMI JTAG controller, which has comprehensive programming for
the ARM, LMI, and unimplemented JTAG instructions.
Preliminary
LM3S102 Data Sheet
27