MD2433-D8G-V3Q18-X-P SanDisk, MD2433-D8G-V3Q18-X-P Datasheet - Page 20

• Manufacturer Part Number: MD2433-D8G-V3Q18-X-P
• Description: IC MDOC H1 8GB 115-FBGA
• Manufacturer: SanDisk

Specifications of MD2433-D8G-V3Q18-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Speed: 64ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 115-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2
2.2.1
The system interface block provides an easy-to-integrate NOR-like (also SRAM and EEPROM-
like) interface to mDOC H1, enabling it to interface with various CPU interfaces, such as a local
bus, NOR interface, SRAM interface, EEPROM interface, or any other compatible interface. In
addition, the interface enables direct access to the Programmable Boot Block to permit XIP
(Execute-In-Place) functionality during system initialization.
A 13-bit wide address bus enables access to the mDOC H1 8KB memory window (as shown in
Section 4.6).
The Chip Enable (CE#), Output Enable (OE#) and Write Enable (WE#) signals trigger read and
write cycles. A write cycle occurs while both the CE# and the WE# inputs are asserted. Similarly, a
read cycle occurs while both the CE# and OE# inputs are asserted. Note that mDOC H1 does not
require a clock signal. It features a unique analog static design, optimized for minimal power
consumption. The CE#, WE# and OE# signals trigger the controller (e.g., system interface block,
bus control and data pipeline) and flash access.
The Reset In (RSTIN#) and Busy (BUSY#) control signals are used in the reset phase.
The Interrupt Request (IRQ#) signal can be used when long I/O operations, such as Block Erase,
delay the CPU. The signal is also asserted when a Data Protection violation has occurred. This
signal frees the CPU to run other tasks, continuing read/write operations with mDOC H1 only after
the IRQ# signal has been asserted and an interrupt handling routine (implemented in the OS) has
been called to return control to the TrueFFS driver.
2.2.2
In this configuration, the address and data signals are multiplexed. The AVD# input is driven by the
host AVD# signal, and the D[15:0] balls, used for both address inputs and data, are connected to the
host AD[15:0] bus. While AVD# is asserted, the host drives AD[11:0] with bits [12:1] of the
address. Host signals AD[15:12] are not significant during this part of the cycle.
This interface is automatically used when a falling edge is detected on AVD#. This edge must occur
after RSTIN# is negated and before the first read or write cycle to the controller.
2.3
The Configuration Interface block enables the designer to configure mDOC H1 to operate in
different modes. The ID[1:0] signals are used in a cascaded configuration (refer to Section 7.6) and
the IF_CFG signal is used to configure 8/16-bit access (refer to Section 7.4.2).
2.4
The Protection and Security-Enabling block, consisting of read/write protection, UID, and an OTP
area, enables advanced data and code security and content protection. Located on the main route of
traffic between the host and the flash, this block monitors and controls all data and code transactions
to and from mDOC H1.
20
System Interface
Standard (NOR-Like) Interface
Multiplexed Interface
Configuration Interface
Protection and Security-Enabling Features
Data Sheet, Rev. 1.1
mDOC H1 4Gb (512MByte) and 8Gb (1GByte)
95-DT-1104-01