MD2433-D8G-V3Q18-X-P SanDisk, MD2433-D8G-V3Q18-X-P Datasheet - Page 59

• Manufacturer Part Number: MD2433-D8G-V3Q18-X-P
• Description: IC MDOC H1 8GB 115-FBGA
• Manufacturer: SanDisk

Specifications of MD2433-D8G-V3Q18-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Speed: 64ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 115-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes: 1. CE# may be asserted any time before or after OE# is asserted. If CE# is asserted after
8.3.5 Power Supply Sequence
When operating mDOC H1 with separate power supplies powering the VCCQ and VCC rails, it is
desirable to turn both supplies on and off simultaneously. Providing power to one supply rail and
not the other (either at power-on or power-off) can cause excessive power dissipation. Damage to
the device may result if this condition persists for more than 500 msec.
8.3.6
mDOC H1 is reset by assertion of the RSTIN# input. When this signal is negated, mDOC H1
initiates a download procedure from the flash memory into the internal Programmable Boot Block.
During this procedure, mDOC H1 does not respond to read or write accesses.
Host systems must therefore observe the requirements described below for first access to mDOC
H1. Any of the following methods may be employed to guarantee first-access timing requirements:
1.
2. Poll the state of the BUSY# output.
3. Use the BUSY# output to hold the host CPU in wait state before completing the first access
Hosts that use mDOC H1 to boot the system must employ option 3 above or use another method to
guarantee the required timing of the first-time access.
59
Use a software loop to wait at least Tp (BUSY1-BUSY1) before accessing the device after the
reset signal is negated.
which will be a RAM read cycle. The data will be valid when BUSY# is negated.
Symbol
t
2. CE# may be negated any time before or after WE# is negated. If CE# is negated before
Power-Up Timing
HO(D)
WE#, all timing relative to WE# asserted will be referenced instead to the time of CE#
asserted.
WE#, all timing relative to WE# negated will be referenced instead to the time of CE#
negated.
D to WE#
WE#
to D hold time
setup time (all other addresses)
Description
Data Sheet, Rev. 1.1
Min
1.65~1.95V
28
2
VCCQ =
mDOC H1 4Gb (512MByte) and 8Gb (1GByte)
Max
Min
28
2.5~3.6V
VCCQ =
2
Max
95-DT-1104-01
Units
nS
nS