MD2433-D8G-V3Q18-X-P SanDisk, MD2433-D8G-V3Q18-X-P Datasheet - Page 25

• Manufacturer Part Number: MD2433-D8G-V3Q18-X-P
• Description: IC MDOC H1 8GB 115-FBGA
• Manufacturer: SanDisk

Specifications of MD2433-D8G-V3Q18-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Speed: 64ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 115-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.1
This is the mode in which standard operations involving the flash memory are performed. Normal
mode is entered when a valid write sequence is sent to the mDOC Control register and Control
Confirmation register. A write cycle occurs when both the CE# and WE# inputs are asserted.
Similarly, a read cycle occurs when both the CE# and OE# inputs are asserted. Because the flash
controller generates its internal clock from these CPU bus signals and some read operations return
volatile data, it is essential that the timing requirements specified in Section 8.3 be met. It is also
essential that read and write cycles not be interrupted by glitches or ringing on the CE#, WE#, and
OE# inputs.
4.2
In Reset mode, mDOC H1 ignores all write cycles, except for those to the mDOC Control register
and Control Confirmation register. All register read cycles return a value of 00H.
Before attempting to perform any operation, the device must be in Normal mode.
4.3
While in Standby mode mDOC H1 power consumption is reduced by disconnecting the internal
clock from the core.
mDOC H1 enters Standby mode after not being accessed during 750ns.
mDOC H1 exits Standby mode and returns to Normal operation mode upon the first host access.
4.4
While in Deep Power-Down mode, mDOC H1’s quiescent power dissipation is reduced by
disabling internal high current consumers (e.g. voltage regulators, oscillator, etc.).
To enter Deep Power-Down mode, a proper sequence must be written to the mDOC H1 Control
registers and the following signals negated (logical ‘1’): CE#, WE#, OE#. All other inputs should
be VSS or VCCQ.
In Deep Power-Down mode, write cycles have no affect and read cycles return indeterminate data
(mDOC H1 does not drive the data bus). Entering Deep Power-Down mode and then returning to
the previous mode does not affect the value of any register.
To exit Deep Power-Down mode, write to the NOP register. The device will exit DPD mode and
enter to Normal mode after 3uS.
Applications that use mDOC H1 as a boot device must ensure that the device is not in Deep Power-
Down mode before reading the Boot vector/instructions. This can be done by pulsing RSTIN# to
the asserted state and waiting for the BUSY# output to be negated.
25
Normal Mode
Reset Mode
Standby Mode
Deep Power-Down Mode
Data Sheet, Rev. 1.1
mDOC H1 4Gb (512MByte) and 8Gb (1GByte)
95-DT-1104-01