MD2433-D8G-V3Q18-X-P SanDisk, MD2433-D8G-V3Q18-X-P Datasheet - Page 36

• Manufacturer Part Number: MD2433-D8G-V3Q18-X-P
• Description: IC MDOC H1 8GB 115-FBGA
• Manufacturer: SanDisk

Specifications of MD2433-D8G-V3Q18-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Speed: 64ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 115-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.9
Description:
Address (hex): 1010H
36
Read/Write
Description
Reset Value
Bit No.
0
1
2
3
4
5
6
7
Interrupt Control Register
Flash Ready Trigger. This bit determines if an interrupt will be generated when the flash
array of mDOC H1 is ready, as follows:
0: Interrupts are disabled – Holds the IRQ# output in the negated state.
1: Interrupt when flash array is ready.
Protection Trigger. When set, an interrupt will be generated upon a data protection
violation.
FIFO Error Trigger. When set, an interrupt will be generated upon a FIFO error: FIFO
overflow or underflow during the data transfer.
EDGE (Edge-sensitive interrupt)
0: Specifies level-sensitive interrupts in which the IRQ# output remains asserted until the
interrupt is cleared.
1: Specifies edge-sensitive interrupts in which the IRQ# output pulses low.
Interrupt Request when flash array is ready. Indicates that the IRQ# output has been
asserted due to an indication that the flash array is ready. Writing 1 to this bit clears its
value, negates the IRQ# output and permits subsequent interrupts to occur.
Interrupt Request on Protection Violation. Indicates that the IRQ# output has been
asserted due to a data protection violation. Writing a 1 to this bit clears its value, negates
the IRQ# output and permits subsequent interrupts to occur.
Interrupt Request on FIFO error. Indicates that FIFO error has happened (FIFO overflow or
underflow) during the data transfer.
Writing a 1 to this bit clears its value, negates the IRQ# output and permits subsequent
interrupts to occur.
Global Interrupt Enable
0: All interrupt sources are disabled and IRQ# output is negated.
1: Interrupt sources enabled and IRQ# is asserted when any enabled interrupt request
condition occurs.
This register controls how interrupts are generated by mDOC H1, and indicates
which of the following three sources has asserted an interrupt:
•
•
•
IRQ_EN
Bit 7
0
Flash array is ready
Data protection violation
Reading or writing more flash data than was expected
IRQ_FE
Bit 6
0
IRQ_P
Bit 5
Data Sheet, Rev. 1.1
0
IRQ_F
Bit 4
Description
0
R/W
EDGE
Bit 3
0
mDOC H1 4Gb (512MByte) and 8Gb (1GByte)
FFER_T
Bit 2
0
PROT_T
Bit 1
0
95-DT-1104-01
FRDY_T
Bit 0
0