MD2433-D8G-V3Q18-X-P SanDisk, MD2433-D8G-V3Q18-X-P Datasheet - Page 22

• Manufacturer Part Number: MD2433-D8G-V3Q18-X-P
• Description: IC MDOC H1 8GB 115-FBGA
• Manufacturer: SanDisk

Specifications of MD2433-D8G-V3Q18-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Speed: 64ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 115-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This feature can be useful when the boot code in the boot partition must be read/write protected.
Upon power-up, the boot code must be unprotected so the CPU can boot directly from mDOC. At
the end of the boot process, protection can be set until the next power-up or reset
2.5
The Programmable Boot Block with XIP functionality enables mDOC H1 to act as a boot device in
addition to performing flash disk data storage functions. This eliminates the need for expensive,
legacy NOR flash or any other boot device on the motherboard.
The Programmable Boot Block on mDOC H1 is 1KB in size. The Download Engine (DE),
described in the next section, expands the functionality of this block by copying the boot code from
the flash into the boot block.
Note: When more than one mDOC H1 device is cascaded, a maximum boot block of 2KB is
2.6
Upon power-up after the rising edge of RSTIN#, the DE automatically downloads the Initial
Program Loader (IPL) to the Programmable Boot Block. The IPL is responsible for starting the
booting process. The download process is quick, and is designed so that when the CPU accesses
mDOC H1 for code execution, the IPL code is already located in the Programmable Boot Block.
During the download process, mDOC H1 does not respond to read or write accesses. Host systems
must therefore observe the requirements described in Section 8.3.6.
In addition, the DE downloads the data protection rules from the flash to the Protection State
Machines (PSM), so that mDOC H1 is secure and protected from the first moment it is active.
During the download process, mDOC H1 asserts (low) the BUSY# signal to indicate to the system
that it is not yet ready to be accessed. Once BUSY# is negated, the system can access mDOC H1.
A failsafe mechanism prevents improper initialization due to a faulty VCC or invalid assertion of
the RSTIN# input. Another failsafe mechanism is designed to overcome possible NAND flash data
errors. It prevents internal registers from powering up in a state that bypasses the intended data
protection. In addition, any attempt to sabotage the data structures causes the entire mDOC to
become both read and write protected, and completely inaccessible.
2.7
Because NAND-based flash is prone to errors, it requires unique error-handling capability.
msystems’ x2 technology implements 4-bit Error Detection Code/Error Correction Code
(EDC/ECC), based on a combination of Bose, Chaudhuri and Hocquenghem (BCH) and Hamming
code algorithms. Error Detection Code (EDC) is implemented in hardware to optimize performance,
while Error Correction Code (ECC) is performed in software, when required, to save silicon costs.
Every time 512-bytes are written, additional parity bits are calculated and written to the flash. Every
time data is read from the flash, the parity bits are read and used to calculate error locations.
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available. The Programmable Boot Block of each device is mapped to a unique address space.
Programmable Boot Block with eXecute In Place (XIP) Functionality
Download Engine (DE)
Error Detection Code/Error Correction Code (EDC/ECC)
Data Sheet, Rev. 1.1
mDOC H1 4Gb (512MByte) and 8Gb (1GByte)
.
95-DT-1104-01