MD2433-D8G-V3Q18-X-P SanDisk, MD2433-D8G-V3Q18-X-P Datasheet - Page 43

no-image

MD2433-D8G-V3Q18-X-P

Manufacturer Part Number
MD2433-D8G-V3Q18-X-P
Description
IC MDOC H1 8GB 115-FBGA
Manufacturer
SanDisk
Datasheet

Specifications of MD2433-D8G-V3Q18-X-P

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
8G (1G x 8)
Speed
64ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-30°C ~ 85°C
Package / Case
115-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MD2433-D8G-V3Q18-X-P
Manufacturer:
SANDISK
Quantity:
18 120
Part Number:
MD2433-D8G-V3Q18-X-P
Manufacturer:
M-SYSTEM
Quantity:
363
Part Number:
MD2433-D8G-V3Q18-X-P
Manufacturer:
SanDisk
Quantity:
10 000
7.5
7.5.1 Hardware Configuration
To configure the hardware for working with the interrupt mechanism, connect the IRQ# ball to the
host interrupt input.
Note: A nominal 10 KΩ pull-up resistor should be connected to this ball.
7.5.2
Configuring the software to support the IRQ# interrupt is performed in two stages.
Stage 1
Configure the software so that when the system is initialized, the following steps occur:
1.
2. The host interrupt is configured to the selected input type, either edge or level-triggered.
3.
4. The interrupt service routine to the host interrupt is connected and enabled.
Stage 2
Configure the software so that for every long flash I/O operation, the following steps occur:
1.
2.
3.
4. The OS either returns control immediately to the TrueFFS driver, or waits for the appropriate
43
The correct value is written to the Interrupt Control register to configure mDOC H1 for:
o
o
Note: Refer to Section 5.9 for further information on the value to write to this register.
The handshake mechanism between the interrupt handler and the OS is initialized.
The correct value is written to the Interrupt Control register to enable the IRQ# interrupt.
Note: Refer to Section 5 for further information on the value to write to this register.
The flash I/O operation starts.
Control is returned to the OS to continue other tasks. When the IRQ# is received, other
interrupts are disabled and the OS is flagged.
condition to return control to the TrueFFS driver.
Implementing the Interrupt Mechanism
Software Configuration
Interrupt source: Flash ready and /or data protection and/or FIFO error
Output type: either edge or level-triggered
Data Sheet, Rev. 1.1
mDOC H1 4Gb (512MByte) and 8Gb (1GByte)
95-DT-1104-01

Related parts for MD2433-D8G-V3Q18-X-P