MD2433-D8G-V3Q18-X-P SanDisk, MD2433-D8G-V3Q18-X-P Datasheet - Page 42

• Manufacturer Part Number: MD2433-D8G-V3Q18-X-P
• Description: IC MDOC H1 8GB 115-FBGA
• Manufacturer: SanDisk

Specifications of MD2433-D8G-V3Q18-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 8G (1G x 8)
• Speed: 64ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 115-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4
7.4.1
When using a standard NOR-like interface, connect the control signals as follows:
•
•
•
•
•
•
•
•
•
•
7.4.2
mDOC H1 can use a multiplexed interface to connect to a CPU with multiplexed bus (asynchronous
read/write protocol). In this configuration, the AVD# input is driven by the host's AVD# signal, and
the D[15:0] balls, used for both address inputs and data, are connected to the host AD[15:0] bus. As
with a standard interface, only address bits [12:0] are significant.
This mode is automatically entered when a falling edge is detected on AVD#. This edge must occur
after RSTIN# is negated and before OE# and CE# are both asserted; i.e., the first read cycle made to
mDOC H1 must observe the multiplexed mode protocol. See Section 8.3 for more information
about the related timing requirements. Please refer to Section 1.2 for ballout and signal descriptions.
42
A[12:0] – Connect these signals to the host’s address signals (see Section 7.8 for
platform-related considerations).
D[15:0] – Connect these signals to the host’s data signals (see Section 7.8 for platform-related
considerations).
Output Enable (OE#) and Write Enable (WE#) – Connect these signals to the host RD# and
WR# signals, respectively.
Chip Enable (CE#) – Connect this signal to the memory address decoder. Most RISC
processors include a programmable decoder to generate various Chip Select (CS) outputs for
different memory zones. These CS signals can be programmed to support different wait states
to accommodate mDOC H1 timing specifications.
Power-On Reset In (RSTIN#) – Connect this signal to the host’s active-low Power-On Reset
signal. Note: The reset circuit should be designed to accommodate system specific requirement
Chip Identification (ID[1:0]) – Connect these signals as shown in. Both signals must be
connected to VSS if the host uses only one mDOC H1. If more than one device is being used,
refer to Section 7.6 for more information on device cascading.
Busy (BUSY#) – This signal indicates when the device is ready for first access after reset. It
may be connected to an input port of the host, or alternatively it may be used to hold the host in
a wait-state condition. The later option is required for hosts that boot from mDOC H1.
Interrupt Request ( IRQ#) – Connect this signal to the host interrupt input.
Lock (LOCK#) – Connect to a logical 0 to prevent the usage of the protection key to open a
protected partition. Connect to logical 1 in order to enable usage of protection keys. Note: If
this feature will not be used then connect LOCK# to VCCQ.
8/16 Bit Interface Configuration (IF_CFG) – This signal is required for configuring the device
for 8- or 16-bit access mode. When low, the device is configured for 8-bit access mode. When
high, 16-bit access mode is selected.
Connecting Control Signals
Standard Interface
Multiplexed Interface
Data Sheet, Rev. 1.1
mDOC H1 4Gb (512MByte) and 8Gb (1GByte)
95-DT-1104-01