DSP56309EVM Freescale Semiconductor, DSP56309EVM Datasheet - Page 145

• Manufacturer Part Number: DSP56309EVM
• Description: KIT EVALUATION FOR XC56309
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of DSP56309EVM

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Description/function: Audio DSPs
• Product: Audio Modules
• For Use With/related Products: DSP56309
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

This section discusses the ESSI registers and describes their bits. Section 7.6, GPIO Signals and
Registers, on page 7-33 covers ESSI GPIO.
7.5.1 ESSI Control Register A (CRA)
The ESSI Control Register A (CRA) is one of two 24-bit read/write control registers that direct
the operation of the ESSI. CRA controls the ESSI clock generator bit and frame sync rates, word
length, and number of words per frame for serial data.
Freescale Semiconductor
Bit Number
PSR
23
11
23
22
—Reserved bit; read as 0; write to 0 for future compatibility.
SSC1
22
10
Bit Name
SSC1
WL2
21
Table 7-3. ESSI Control Register A (CRA) Bit Definitions
9
Reset Value
Figure 7-2. ESSI Control Register A(CRA)
WL1
20
8
0
0
(ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5)
WL0
PM7
DSP56309 User’s Manual, Rev. 1
19
7
Reserved. Write to 0 for future compatibility.
Select SC1
Controls the functionality of the SC1 signal. If SSC1 is set, the ESSI is
configured in Synchronous mode (the CRB synchronous/asynchronous bit
(SYN) is set), and transmitter 2 is disabled (transmit enable (TE2) = 0), then
the SC1 signal acts as the transmitter 0 driver-enabled signal while the SC1
signal is configured as output (SCD1 = 1). This configuration enables an
external buffer for the transmitter 0 output. If SSC1 is cleared, the ESSI is
configured in Synchronous mode (SYN = 1), and transmitter 2 is disabled
(TE2 = 0), then the SC1 acts as the serial I/O flag while the SC1 signal is
configured as output (SCD1 = 1).
PM6
ALC
18
6
PM5
17
5
PM4
DC4
16
4
Description
DC3
PM3
15
3
DC2
PM2
14
ESSI Programming Model
2
PM1
DC1
13
1
DC0
PM0
12
0
7-13