DSP56309EVM Freescale Semiconductor, DSP56309EVM Datasheet - Page 167

KIT EVALUATION FOR XC56309

DSP56309EVM

Manufacturer Part Number
DSP56309EVM
Description
KIT EVALUATION FOR XC56309
Manufacturer
Freescale Semiconductor
Type
DSPr
Datasheets

Specifications of DSP56309EVM

Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Description/function
Audio DSPs
Product
Audio Modules
For Use With/related Products
DSP56309
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
signal line. If a port signal PC[i] or PD[i] is configured as an output (GPO), a value written to the
corresponding PDRC[i] pr PDRD[i] bit is reflected as a value on the output signal line. Either a
hardware
Freescale Semiconductor
Note:
23
11
Figure 7-20. Port Data Registers (PDRC X:$FFFFBD) (PDRD X: $FFFFAD)
RESET
For bits 5–0, the value represents the level that is written to or read from the associated signal line if it is
enabled as a GPIO signal by the respective port control register (PCRC or PCRD) bits. For ESSI0, the GPIO
signals are PC[5–0]. For ESSI1, the GPIO signals are PD[5–0]. The corresponding data bits for Port C
GPIOs are PDRC[5–0]. The corresponding data bits for Port D GPIOs are PDRD[5–0].
= Reserved. Read as zero. Write with zero for future compatibility.
22
10
signal or a software RESET instruction clears all PDRC and PDRD bits.
21
9
20
8
DSP56309 User’s Manual, Rev. 1
19
7
18
6
PDRx5
17
5
PDRx4
16
4
PDRx3
15
3
PDRx2
14
GPIO Signals and Registers
2
PDRx1
13
1
PDRx0
12
0
7-35

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