DSP56309EVM Freescale Semiconductor, DSP56309EVM Datasheet - Page 271

• Manufacturer Part Number: DSP56309EVM
• Description: KIT EVALUATION FOR XC56309
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of DSP56309EVM

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Description/function: Audio DSPs
• Product: Audio Modules
• For Use With/related Products: DSP56309
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DMA Destination Space (DDS) bit 4-33
DMA Interrupt Enable (DIE) bit 4-28
DMA Request Source (DRS) bit 4-32
DMA Source Space (DSS) bit 4-33
DMA Three-Dimensional Mode (D3D) bit 4-32
DMA Transfer Mode (DTM) bit 4-29
DO FOREVER (FV) Flag bit 4-9
DO loop 1-8
Do Loop Flag (LF) bit 4-9
double data strobe mode 2-2
Double Host Request (HDRQ) bit 6-8
Double-Precision Multiply Mode (DM) bit 4-9
DRAM Control Register (DCR) 4-21
DSP core
DSP56300
DSP56309
DSP-to-host
dynamic memory configuration switching 3-5
E
Enhanced Synchronous Serial Interface (ESSI) 1-12
Freescale Semiconductor
DMA Channel Enable (DE) 4-28
DMA Channel Priority (DPR) 4-30
DMA Continuous Mode Enable (DCON) 4-31
DMA Destination Space (DDS) 4-33
DMA Interrupt Enable (DIE) 4-28
DMA Request Source (DRS) 4-32
DMA Source Space (DSS) 4-33
DMA Three-Dimensional Mode (D3D) 4-32
DMA Transfer Mode (DTM) 4-29
Bit Definitions 4-24
Bus Column In-Page Wait State (BCW) 4-25
Bus DRAM Page Size (BPS) 4-25
Bus Mastership Enable (BME) 4-25
Bus Page Logic Enable (BPLE) 4-25
Bus Refresh Enable (BREN) 4-24
Bus Refresh Prescaler (BRP) 4-24
Bus Refresh Rate (BRF) 4-24
Bus Row Out-of-Page Wait States (BRW) 4-25
Bus Software Triggered Reset (BSTR) 4-24
programming sheet B-15
programming model 6-11
core 1-1
Family Manual 1-1
Technical Data 1-1
data word 6-2
handshaking protocols 6-2
interrupts 6-2
mapping 6-2
transfer modes 6-2
transfers 6-5
2-16
24-bit fractional data 7-14
after reset 7-6
,
2-17
,
7-1
,
6-19
,
1-4
,
6-8
,
,
4-23
6-23
DSP56309 User’s Manual, Rev. 1
,
2-2
,
Asynchronous mode 7-3
audio enhancements 7-2
byte format 7-11
clock generator 7-10
Clock Sources 7-3
codec 7-11
control and time slot registers 7-6
control direction of SC2 I/O signal 7-21
Control Register A (CRA)
Control Register B (CRB)
control registers 7-12
data and control signals 7-2
DMA 7-6
exception configuration 7-8
exceptions 7-7
flags 7-12
frame rate divider 7-9
frame sync
Alignment Control (ALC) 7-14
Frame Rate Divider Control (DC) 7-15
Prescale Modulus Select (PM) 7-15
Prescaler Range (PSR) 7-15
programming sheet B-23
Select SCK (SSC1) 7-13
Word Length Control (WL) 7-14
Clock Polarity (CKP) 7-20
Clock Source Directions (SCKD) 7-21
Frame Sync Length (FSL) 7-21
Frame Sync Polarity (FSP) 7-20
Frame Sync Relative Timing (FSR) 7-21
Mode Select (MOD) 7-20
programming sheet B-24
Receive Enable (RE) 7-19
Receive Exception Interrupt Enable (REIE) 7-18
Receive Interrupt Enable (RIE) 7-18
Receive Last Slot Interrupt Enable 7-18
Serial Control Direction 0 (SCD0) 7-22
Serial Control Direction 1 (SCD1) 7-22
Serial Control Direction 2 (SCD2) 7-21
Serial Output Flag 0 (OF0) 7-22
Serial Output Flag 1 (OF1) 7-22
Shift Direction (SHFD) 7-21
Synchronous/Asynchronous (SYN) 7-20
Transmit 0 Enable (TE0) 7-19
Transmit 1 Enable (TE1) 7-19
Transmit 2 Enable (TE2) 7-20
Transmit Exception Interrupt Enable (TEIE) 7-18
Transmit Interrupt Enable (TIE) 7-18
Transmit Last Slot Interrupt Enable (TLIE) 7-18
receive last slot interrupt 7-7
transmit data 7-8
transmit data with exception status 7-7
transmit last slot interrupt 7-7
generator 7-16
length 7-10
,
7-16
,
7-4
,
7-10
,
7-19
Index-3
Index