S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet
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MC9S12HY64 Reference Manual Covers MC9S12HY/HA Family S12 Microcontrollers MC9S12HY64RMV1 Rev. 1.04 11/2010 freescale.com ...
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To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ ...
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... KByte Flash Module (S12FTMRC64K1V1 613 Chapter 18 Liquid Crystal Display (LCD40F4BV1 663 Chapter 19 Motor Controller (MC10B8CV1 685 Appendix A Electrical Characteristics 717 Appendix B Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 Appendix C Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 Appendix D PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 Appendix E Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 3 ...
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... Appendix F Detailed Register Address Map 764 MC9S12HY/HA-Family Reference Manual, Rev. 1.04 4 Freescale Semiconductor ...
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... Implemented Memory in the System Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 3.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 4.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Chapter 1 Chapter 2 Chapter 3 Chapter 4 Interrupt Module (S12SINTV1) 5 ...
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... Freescale’s Scalable Controller Area Network (S12MSCANV3) 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 9.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 9.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 9.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 MC9S12HY/HA-Family Reference Manual, Rev. 1.04 6 Chapter 5 Chapter 6 Debug Module (S12SDBGV2) Chapter 7 Chapter 8 Chapter 9 Freescale Semiconductor ...
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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 14.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 14.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Chapter 10 Inter-Integrated Circuit (IICV3) Chapter 11 Chapter 12 Chapter 13 Chapter 14 Timer Module (TIM16B8CV2) ...
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... Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 18.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 19.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 19.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 MC9S12HY/HA-Family Reference Manual, Rev. 1.04 8 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Motor Controller (MC10B8CV1) Freescale Semiconductor ...
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... A.12 LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 A.13 MSCAN 747 A.14 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 A.14.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 A.14.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 C.1 100-Pin LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Appendix A Electrical Characteristics Appendix B Ordering Information Appendix C Package Information ...
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... C.2 64-Pin LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756 E.1 Memory Sizes and Package Options S12HY/S12HA - Family . . . . . . . . . . . . . . . . . . . . . . . . . . 763 MC9S12HY/HA-Family Reference Manual, Rev. 1.04 10 Appendix D PCB Layout Guidelines Appendix E Derivative Differences Appendix F Detailed Register Address Map Freescale Semiconductor ...
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... LQFP and 64-pin LQFP package options. In addition to the I/O ports available in each module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes. 1.2 Features This section describes the key features of the MC9S12HY/HA family. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 11 ...
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... Kbytes 64 100 64 100 16-bit 16-bit 8-bit x16-bit 20x4 40x4 20x4 40x4 20x4 Yes Yes Yes 4.5 V – 5.5 V Yes MC9S12 MC9S12 MC9S12 HA32 HA48 HA64 32 Kbytes 48 Kbytes 64 Kbytes 2 Kbytes 4 Kbytes 4 Kbytes 64 100 64 100 40x4 20x4 40x4 20x4 Freescale Semiconductor 100 40x4 22 ...
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... Extensive set of indexed addressing capabilities, including: — Using the stack pointer as an indexing register in all indexed operations — Using the program counter as an indexing register in all but auto increment/decrement mode MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Device Overview MC9S12HY/HA-Family 13 ...
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... Internal RC Oscillator (IRC) • Trimmable internal reference clock. — Frequency: 1 MHz — Trimmed accuracy over –40˚C to +125˚C ambient temperature range: 2.0% — Trimmed accuracy over –40˚C to +85˚C ambient temperature range: 1.5% MC9S12HY/HA-Family Reference Manual, Rev. 1.04 14 Freescale Semiconductor ...
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... Timer (TIM1) • 16-bit channels for input capture • 16-bit channels for output compare • 16-bit free-running counter with 7-bit precision prescaler • 16-bit pulse accumulator MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Device Overview MC9S12HY/HA-Family 15 ...
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... Programmable bit rate Mbps • Five receive buffers with FIFO storage scheme • Three transmit buffers with internal prioritization • Flexible identifier acceptance filter programmable as: — 32-bit — 16-bit MC9S12HY/HA-Family Reference Manual, Rev. 1.04 16 Freescale Semiconductor ...
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... Internal oscillator for conversion in stop modes — Wakeup from low power modes on analog comparison > or <= match — Continuous conversion mode — Multiple channel scans • Pins can also be used as digital I/O MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Device Overview MC9S12HY/HA-Family 17 ...
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... Two types of comparator matches — Tagged This matches just before a specific instruction begins execution — Force This is valid on the first instruction boundary after a match occurs • Four trace modes • Four stage state sequencer MC9S12HY/HA-Family Reference Manual, Rev. 1.04 18 Freescale Semiconductor ...
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... PV7 VLCD 5V IO Supply VDDX/VSSX VDDM1/VSSM1 VDDM2/VSSM2 VDDA/VSSA Figure 1-1. MC9S12HY/HA-Family 100 LQFP Block Diagram MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 2K/4K bytes RAM Voltage Regulator CPU12-V1 Debug Module 3 address breakpoints 1 data breakpoints 64 Byte Trace Buffer Clock Monitor COP Watchdog Periodic Interrupt Auto ...
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... SCI (serial communications interface) Reserved SPI (serial peripheral interface) IIC (Inter IC bus) Reserved FTMRC control registers Reserved INT (interrupt module) Reserved CAN Reserved MC (motor controller) LCD Reserved PIM (port integration module) TIM1 (timer module) Reserved CPMU (clock and power management) Size (Bytes Freescale Semiconductor ...
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... Table 1-4. MC9S12HY/MC9S12HA Derivatives Feature P-Flash size PF_LOW PPAGES RAMSIZE RAM_LOW MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Module Reserved NOTE Table 1-2 is not allocated to any module. shows S12HY/HA family CPU and BDM local address translation Local 64K memory map Global 256K memory map ...
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... MC9S12HY/HA-Family Reference Manual, Rev. 1.04 22 0x0_0000 RAM_LOW 0x0_4000 0x0_4400 0x0_5400 PF_LOW=0x0_8000 PF_LOW=0x3_0000 PPAGE PF_LOW=0x3_4000 PF_LOW=0x3_8000 PF_LOW=0x3_C000 0x3_FFFF Global Memory Map REGISTERS Unimplemented Area RAM NVM Resources D-Flash NVM Resources P-Flash 10 *16K paged Unpaged P-Flash Unpaged P-Flash Unpaged P-Flash Unpaged P-Flash Freescale Semiconductor ...
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... CPU and BDM Local Memory Map 0x0000 REGISTERS 0x0400 D-Flash 0x1400 Reserved RAM 0x4000 Unpaged P-Flash 0x8000 Unpaged P-Flash or P-Flash window 0xC000 Unpaged P-Flash 0xFFFF MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 0x0_0000 RAM_LOW 0x0_4000 0x0_4400 0x0_5400 PF_LOW=0x0_8000 PF_LOW=0x3_0000 PPAGE PF_LOW=0x3_4000 PF_LOW=0x3_8000 ...
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... MC9S12HY/HA-Family Reference Manual, Rev. 1.04 24 0x0_0000 RAM_LOW 0x0_4000 0x0_4400 0x0_5400 PF_LOW=0x0_8000 PF_LOW=0x3_0000 PPAGE PF_LOW=0x3_4000 PF_LOW=0x3_8000 PF_LOW=0x3_C000 0x3_FFFF Global Memory Map REGISTERS Unimplemented Area RAM NVM Resources D-Flash NVM Resources P-Flash 10 *16K paged Unpaged P-Flash Unpaged P-Flash Unpaged P-Flash Unpaged P-Flash Freescale Semiconductor ...
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... This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals built from the signal description sections of the individual IP blocks on the device. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Table 1-5. Assigned Part ID Numbers (1) Mask Set Number ...
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... PH4 / FP23 62 VDDX 61 VSSX 60 PH3 / SS / SDA / FP22 59 PH2 / ECLK / SCK / FP21 58 PH1 / MOSI / FP20 57 PH0 / MISO / SCL / FP19 56 PR6 / SCL / FP18 55 PR5 / SDA / FP17 54 PT7 / IOC0_7 / KWT7 / FP16 53 PT6 / IOC0_6 / KWT6 / FP15 52 PT5 / IOC0_5 / KWT5 / FP14 51 PT4 / IOC0_4 / KWT4 / FP13 Freescale Semiconductor ...
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... M1C1M / IOC0_3 / PU6 M1C1P / PU7 M2C0M / IOC1_0 / SCL / PWM4 / MISO / PV0 M2C0P / MOSI / PWM5 / PV1 M2C1M / IOC1_1 / SCK / PWM6 / PV2 M2C1P / SDA / PWM7 / SS / PV3 RXD / PWM6 / PS0 Figure 1-6. MC9S12HY/HA-Family 64 LQFP pinout MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor TEST MC9S12HY/HA- ...
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... MC9S12HY/HA-Family Reference Manual, Rev. 1.04 28 1-7. Port 100 LQFP 8/8 Port A 8 Port B 8 Port H 8 Port P 8 Port R 8 Port S 8 Port T 8 Port U 8 Port V 8 Sum of Ports 80 2/2 1/1 (1) 1/1 1/1 1 VLCD power 1 64 LQFP 6 1/1 1/1 1/1 1/1 ( Freescale Semiconductor ...
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... Table 1-8 provides a pin out summary listing the availability and functionality of individual pins for each package option. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor TIM1(IO PWM[7: SPI C7/6) ...
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Package Function Pin LQ LQ 2nd 3rd FP FP Pin Func. Func. 100 TEST — — 2 — NC — — PU0 IOC0_0 M0C0M 4 3 PU1 M0C0P — PU2 IOC0_1 M0C1M 6 ...
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Package Function Pin LQ LQ 2nd 3rd FP FP Pin Func. Func. 100 PV1 MOSI PWM5 15 14 PV2 SCK PWM6 16 15 PV3 SS PWM7 17 — VDDM2 — — 18 — VSSM2 — — 19 ...
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Package Function Pin LQ LQ 2nd 3rd FP FP Pin Func. Func. 100 PS3 TXCAN — 29 — PS4 PWM0 SCL 30 — PS5 PWM1 KWS5 31 — PS6 PWM2 KWS6 32 — PS7 PWM3 SDA 33 ...
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Package Function Pin LQ LQ 2nd 3rd FP FP Pin Func. Func. 100 64 41 — PP4 PWM4 FP4 42 — PP5 PWM5 FP5 43 — PP6 PWM6 FP6 44 — PP7 PWM7 FP7 45 28 PT0 IOC1_4 KWT0 46 ...
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Package Function Pin LQ LQ 2nd 3rd FP FP Pin Func. Func. 100 PT5 IOC0_5 KWT5 53 35 PT6 IOC0_6 KWT6 54 36 PT7 IOC0_7 KWT7 55 — PR5 SDA FP17 56 — PR6 SCL FP18 57 ...
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Package Function Pin LQ LQ 2nd 3rd FP FP Pin Func. Func. 100 64 64 — PH5 FP24 — 65 — PH6 FP25 — 66 — PH7 FP26 — 67 — PR7 FP27 — 68 — PB0 FP28 — 69 ...
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Package Function Pin LQ LQ 2nd 3rd FP FP Pin Func. Func. 100 64 78 — PA4 FP33 — 79 — PA5 FP34 — 80 — PA6 FP35 — 81 — PA7 FP36 — 82 — PB1 FP37 — 83 ...
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Package Function Pin LQ LQ 2nd 3rd FP FP Pin Func. Func. 100 VDDA VRH — PAD00 AN00 KWAD0 94 60 PAD01 AN01 KWAD1 95 61 PAD02 AN02 KWAD2 96 62 PAD03 AN03 KWAD3 97 ...
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... PA1 is a general-purpose input or output pin. It can be configured as frontplane segment driver outputs FP[30]. It also provide the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode. The XIRQ interrupt MC9S12HY/HA-Family Reference Manual, Rev. 1.04 38 NOTE in all applications. SSA Freescale Semiconductor ...
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... SCL as IIC module.It can be configured as PWM channel0 1.7.3.16 PS3 / TXCAN — Port S I/O Pin 3 PS3 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the scalable controller area network controller (CAN). MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Device Overview MC9S12HY/HA-Family 39 ...
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... The can be configured as keypad wakeup inputs. 1.7.3.25 PR[1:0] / IOC0[7:6] / KWR[1:0] — Port R I/O Pins [1:0] PR[1:0] are a general-purpose input or output pins. They can be configured as timer (TIM0) channels 7-6. They can be configured as keypad wakeup inputs. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 40 Freescale Semiconductor ...
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... PT[7:4] / IOC0[7:4] / KWT[7:4] / FP[16:13] — Port T I/O Pins [7:4] PT[7:4] are a general-purpose input or output pins. They can be configured as frontplane segment driver outputs FP[16:13]. They can be configured as timer (TIM0) channels 7-4. They can be configured as key wakeup inputs. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Device Overview MC9S12HY/HA-Family 41 ...
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... The pin interfaces to the coils of motor 0. It can aslo be configured as timer(TIM0) channel 1 1.7.3.40 PU[1] / M0C0P— Port U I/O Pin [1] PU[ general-purpose input or output pin. It can be configured as high current PWM output pin which can be used for motor drive. The pin interfaces to the coils of motor 0. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 42 Freescale Semiconductor ...
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... PV1 is a general-purpose input or output pin. It can be configured as high current PWM output pin which can be used for motor driver. It interface to the coil of motor 2. It can be configured as the master output MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Device Overview MC9S12HY/HA-Family 43 ...
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... Regulator and ATD Reference Voltage inputs These are the power supply and ground input pins for Port AD IO, the analog-to-digital converter and the voltage regulator. And also server as the reference voltage input pins for the analog-to-digital converter. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 44 NOTE Freescale Semiconductor ...
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... System Clock Description For the system clock description please refer to chapter Management Unit (S12CPMU) Block Frame Frequency always connected to the internal 1MHZ RC output. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Nominal Description Voltage 5.0 V External power supply to internal voltage regulator 5 ...
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... The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to Section 5.4.1 Security and Section 17.5 Security MC9S12HY/HA-Family Reference Manual, Rev. 1.04 46 1.9.1 Chip Configuration 1.9.2 Low Power Operation. Table 1-10. Chip Modes Chip Modes MODC Normal single chip 1 Special single chip 0 Summary. Table 1-10). Freescale Semiconductor ...
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... Vector base + 0xEC Vector base+ 0xEA Vector base+ 0xE8 Vector base+ 0xE6 Vector base + 0xE4 Vector base+ 0xE2 MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Reset Source Power-On Reset (POR) Low Voltage Reset (LVR) External pin RESET Illegal Address Reset Clock monitor reset ...
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... PIEAD (PIEAD7-PIEAD0) PIER (PIER3-PIER0) PIES (PIES6-PIES5) CPMUINT(OSCIE) CPMUINT(LOCKIE) IBCR(IBIE) FCNFG2 (SFDIE, DFDIE) FCNFG (CCIE) CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE) CANTIER (TXEIE[2:0]) TIM1TIE (C0I) TIM1TIE (C1I) TIM1TIE (C2I) TIM1TIE (C3I) TIM1TIE (C4I) TIM1TIE (C5I) TIM1TIE (C6I) TIM1TIE (C7I) Freescale Semiconductor ...
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... I/O Pins Refer to the PIM section for reset configurations of all peripheral module ports. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Interrupt Source TIM1 timer overflow Reserved Motor Control Timer Overflow ...
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... COPCTL Register 1 0 Table 1-15 Table 1-15. ATD External Trigger Sources Connectivity (1) PP1 1 PP3 TIM0 Channel output 2 TIM0 Channel output 3 for coding. The FOPT register is 111 110 101 100 011 010 001 000 0 1 shows the connection of the external (2) 2 Freescale Semiconductor ...
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... Please do not confuse them with the S12HY/S12HA product families. S12HY/S12HA will support only 10-bit ATD resolution, although in ATD12B8C block it still has the 12- bit descriptions. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor and the output voltage of the temperature sensor V BG Device Overview MC9S12HY/HA-Family can be ...
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... Device Overview MC9S12HY/HA-Family MC9S12HY/HA-Family Reference Manual, Rev. 1.04 52 Freescale Semiconductor ...
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... Port U/V associated with the Motor driver output. Also PV3-0 associated with 1 SPI, 1 IIC and 4 PWM channels. PU0/PU2/PU4/PU6 and PV0/PV2/PV4/PV6 associated with TIM0 channels 0 -3 and TIM1 channels 0 -3 MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Author Description of Changes Initial version ...
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... Optional features supported on dedicated pins: • Open drain for wired-or connections • Interrupt inputs with glitch filtering • The output slew rate control 2.2 External Signal Description This section lists and describes the signals that do connect off-chip. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 54 NOTE Freescale Semiconductor ...
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... PA[0] FP[29] IRQ GPIO B PB[7:4] BP[3:0] GPIO PB[3:0] FP[39:37,28] GPIO MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor NOTE Table 2-1. Pin Functions and Priorities I/O Description I MODC input during RESET I/O BDM communication pin I ATD analog I Key Wakeup I/O General purpose ...
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... I/O General purpose I LCD frontplane segment driver output I/O General purpose I Key Wakeup I/O TIM1 channel, mappable through software I/O General purpose I Key Wakeup I/O TIM0 channel, mappable through software I/O General purpose Pin Function after Reset GPIO GPIO GPIO Freescale Semiconductor ...
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... T PT[7:4] FP[16:13] KWT[7:4] IOC0[7:4] GPIO PT[3:0] FP[11:8] KWT[3:0] IOC1[7:4] GPIO MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor I/O Description I SPI I/O SDA of IIC O PWM channel 3, mappable through software I/O General purpose I Key Wakeup I/O SCK of SPI O PWM channel 2, mappable through software ...
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... Motor control output for motor 0 I/O General purpose O Motor control output for motor 0 I/O TIM0 channel 1 I/O General purpose O Motor control output for motor 0 I/O General purpose O Motor control output for motor 0 I/O TIM0 channel 0 I/O General purpose Pin Function after Reset GPIO Freescale Semiconductor ...
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... Signals in brackets denote alternative module routing pins. 2 Function active when RESET asserted. 2.3 Memory Map and Register Definition This section provides a detailed description of all Port Integration Module registers. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor I/O Description O Motor control output for motor 3 I/O General purpose O ...
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... R/W 0x43 2.3.8/2-74 R/W 0x00 2.3.9/2- R/W 0x80 2.3.10/2-77 R 0x00 2.3.11/2-77 2 R/W 0x00 2.3.12/2-78 R 0x00 2.3.13/2- R/W 0x00 2.3.14/2- 2.3.15/2-80 R/W 0x00 2.3.16/2-81 R/W 0x00 2.3.17/2-81 R/W 0xFF 2.3.18/2-82 R/W 0xFF 2.3.19/2-82 R 0x00 2.3.20/2-83 R/W 0x00 2.3.21/2-83 Freescale Semiconductor ...
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... PPSH—Port H Polarity Select Register 0x0266 WOMH—Port H Wired-Or Mode Register 0x0267 PIM Reserved 0x0268 PIM Reserved : 0x026F MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Table 2-2. Block Memory Map (continued) Register Port Integration Module (S12HYPIMV1) Access Reset Value Section/Page R/W 0x00 2.3.22/2- ...
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... R/W 0x00 2.3.60/2-110 R/W 0xFF 2.3.61/2-110 R/W 0xFF 2.3.62/2-111 R/W 0x00 2.3.63/2-111 R 0x00 2.3.64/2-112 R/W 0x00 2.3.65/2-112 R/W 0x00 2.3.66/2-112 R/W 0x00 2.3.67/2-113 R/W 0x00 2.3.68/2-113 R/W 0x00 2.3.69/2-114 R/W 0x00 2.3.70/2-114 R/W 0x00 2.3.71/2-115 R/W 0x00 2.3.72/2-115 Freescale Semiconductor ...
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... DDRA7 DDRA6 DDRA W 0x0003 R DDRB7 DDRB6 DDRB W 0x0004 -0x0009 W Reserved = Unimplemented or Reserved MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Table 2-2. Block Memory Map (continued) Register 5 4 PA5 PA4 PA3 PB5 PB4 PB3 DDRA5 DDRA4 DDRA3 DDRB5 DDRB4 DDRB3 0 0 Port Integration Module (S12HYPIMV1) ...
Page 64
... XIRQEN Non-PIM Address Range PTT5 PTT4 PTT3 PTIT5 PTIT4 PTIT3 DDRT5 DDRT4 DDRT3 RDRT5 RDRT4 RDRT3 2 1 Bit 0 0 PUPBE PUPAE 0 RDPB RDPA EDIV2 EDIV1 EDIV0 PTT2 PTT1 PTT0 PTIT2 PTIT1 PTIT0 DDRT2 DDRT1 DDRT0 RDRT2 RDRT1 RDRT0 Freescale Semiconductor ...
Page 65
... PTSRR W 0x0250 -0x0257 W Reserved 0x0258 R PTP7 PTP6 PTP W 0x0259 R PTIP7 PTIP6 PTIP W = Unimplemented or Reserved MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor PERT5 PERT4 PERT3 PPST5 PPST4 PPST3 PTTRR5 PTTRR4 PTS5 PTS4 PTS3 PTIS5 PTIS4 PTIS3 DDRS5 DDRS4 DDRS3 RDRS5 RDRS4 ...
Page 66
... Bit 0 DDRP2 DDRP1 DDRP0 RDRP2 RDRP1 RDRP0 PERP2 PERP1 PERP0 PPSP2 PPSP1 PPSP0 0 PTPRRH1 PTPRRH0 PTPRRL2 PTPRRL1 PTPRRL0 PTH2 PTH1 PTH0 PTIH2 PTIH1 PTIH0 DDRH2 DDRH1 DDRH0 RDRH2 RDRH1 RDRH0 PERH2 PERH1 PERH0 PPSH2 PPSH1 PPSH0 WOMH2 WOMH1 WOMH0 Freescale Semiconductor ...
Page 67
... DDRR6 DDRR W 0x0283 R RDRR7 RDRR6 RDRR W 0x0284 R PERR7 PERR6 PERR W 0x0285 R PPSR7 PPSR6 PPSR W 0x0286 R WOMR7 WOMR6 WOMR W = Unimplemented or Reserved MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor PT1AD5 PT1AD4 PT1AD3 DDR1AD5 DDR1AD4 DDR1AD3 RDR1AD5 RDR1AD4 RDR1AD3 PER1AD5 PER1AD4 PER1AD3 PTR5 PTR4 ...
Page 68
... SRRU3 2 1 Bit PIET2 PIET1 PIET0 PIFT2 PIFT1 PIFT0 PIE1AD2 PIE1AD1 PIE1AD0 PIF1AD2 PIF1AD1 PIF1AD0 PIER2 PIER1 PIER0 PIFR2 PIFR1 PIFR0 PTU2 PTU1 PTU0 PTIU2 PTIU1 PTIU0 DDRU2 DDRU1 DDRU0 PERU2 PERU1 PERU0 PPSU2 PPSU1 PPSU0 SRRU2 SRRU1 SRRU0 Freescale Semiconductor ...
Page 69
... The configuration bit PS is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pull-up or pull-down device active. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor ...
Page 70
... Disabled Pull Up Disabled Pull Down Disabled Disabled Falling edge Disabled Rising edge Pull Up Falling edge Pull Down Rising edge Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Falling edge Disabled Rising edge Disabled Falling edge Disabled Rising edge Freescale Semiconductor ...
Page 71
... The LCD segment driver output takes precedence over the IRQ and general purpose I/O function if the related LCD segment is enabled. • The IRQ takes precedence over the general purpose I/O function if the IRQ function is enabled MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor ...
Page 72
... Read: Anytime Write: Anytime MC9S12HY/HA-Family Reference Manual, Rev. 1. PB5 PB4 PB3 BP1 BP0 FP39 Figure 2-2. Port B Data Register (PORTB) Description DDRA5 DDRA4 DDRA3 Access: User read/write PB2 PB1 PB7 FP38 FP37 FP28 Access: User read/write DDRA2 DDRA1 DDRA0 Freescale Semiconductor 1 1 ...
Page 73
... DDRB7 DDRB6 W Reset 0 0 Figure 2-4. Port B Data Direction Register (DDRB) 1 Read: Anytime Write: Anytime MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Table 2-6. DDRA Register Field Descriptions Description 5 4 DDRB5 DDRB4 DDRB3 0 0 Port Integration Module (S12HYPIMV1) Access: User read/write ...
Page 74
... Figure 2-6. Ports AB, BKGD pin Pull Control Register (PUCR) 1 Read:Anytime in single-chip modes. Write:Anytime, except BKPUE which is writable in Special Single-Chip Mode only. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 74 Table 2-7. DDRB Register Field Descriptions Description NOTE Figure 2-5. PIM Reserved Register Access: User read Access: User read/write PUPBE Freescale Semiconductor PUPAE 1 ...
Page 75
... Ports A, B Reduced Drive Register (RDRIV) Address 0x000D (PRR Reset Unimplemented or Reserved Figure 2-7. Ports ABEK Reduced Drive Register (RDRIV) 1 Read: Anytime Write: Anytime MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Table 2-8. PUCR Register Field Descriptions Description Port Integration Module (S12HYPIMV1) Access: User read/write RDPB ...
Page 76
... This bit configures the drive strength of all associated port output pins as either full or reduced pin is used as input this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin. 1 Reduced drive selected (1/6 of the full drive strength) 0 Full drive strength enabled MC9S12HY/HA-Family Reference Manual, Rev. 1.04 76 Description Freescale Semiconductor ...
Page 77
... ECLK rate = bus clock rate divided by 3,... 11111 ECLK rate = bus clock rate divided by 32 2.3.11 PIM Reserved Register Address 0x001D (PRR Reset Unimplemented or Reserved Freescale Semiconductor 5 4 DIV16 EDIV4 0 0 Figure 2-8. ECLK Control Register (ECLKCTL) Description Figure 2-9. PIM Reserved Register MC9S12HY/HA-Family Reference Manual, Rev ...
Page 78
... XIRQ pin is disconnected from interrupt logic 2.3.13 PIM Reserved Register This register is reserved for factory testing of the PIM module and is not available in normal operation. MC9S12HY/HA-Family Reference Manual, Rev. 1. XIRQEN Figure 2-10. IRQ Control Register (IRQCR) Description 1 Access: User read/write Freescale Semiconductor ...
Page 79
... Address 0x0240 PTT7 PTT6 W IOC0_7 IOC0_6 Altern. FP16 FP15 Function Reset Read: Anytime. The data source is depending on the data direction value. Write: Anytime MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Figure 2-11. PIM Reserved Register PTT5 PTT4 PTT3 IOC0_5 IOC0_4 IOC1_7 ...
Page 80
... MC9S12HY/HA-Family Reference Manual, Rev. 1.04 80 Table 2-12. PTT Register Field Descriptions Description 5 4 PTIT5 PTIT4 PTIT3 Unaffected by reset Figure 2-13. Port T Input Register (PTIT) Table 2-13. PTIT Register Field Descriptions Description Access: User read PTIT2 PTIT1 Freescale Semiconductor 1 0 PTIT0 u ...
Page 81
... Port T Reduced Drive Register (RDRT) Address 0x0243 RDRT7 RDRT6 W Reset 0 0 Figure 2-15. Port T Reduced Drive Register (RDRT) MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 5 4 DDRT5 DDRT4 DDRT3 0 0 Table 2-14. DDRT Register Field Descriptions Description NOTE 5 4 RDRT5 ...
Page 82
... MC9S12HY/HA-Family Reference Manual, Rev. 1.04 82 Table 2-15. RDRT Register Field Descriptions Description 5 4 PERT5 PERT4 PERT3 1 1 Table 2-16. PERT Register Field Descriptions Description 5 4 PPST5 PPST4 PPST3 1 1 Access: User read/write PERT2 PERT1 Access: User read/write PPST2 PPST1 Freescale Semiconductor 1 0 PERT0 PPST0 1 ...
Page 83
... Option Reset Unimplemented or Reserved 1 Read: Anytime Write: Anytime This register configures the re-routing of TIM0/1 channels on alternative pins on Port R/T. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Table 2-17. PPST Register Field Descriptions Description Figure 2-18. PIM Reserved Register 5 4 PTTRR5 ...
Page 84
... MC9S12HY/HA-Family Reference Manual, Rev. 1.04 84 Description PTS5 PTS4 PTS3 PWM1 PWM0 — — SCL — MOSI MISO TXCAN Figure 2-20. Port S Data Register (PTS) Access: User read/write PTS2 PTS1 PTS0 — PWM7 PWM6 — — — RXCAN TXD RXD Freescale Semiconductor 1 ...
Page 85
... If the associated data direction bit is set read returns the value of the port register bit, otherwise the buffered pin input state is read. • The CAN takes precedence over the general purpose I/O function if enabled MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Table 2-19. PTS Register Field Descriptions Description Port Integration Module (S12HYPIMV1) ...
Page 86
... This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 86 Description 5 4 PTIS5 PTIS4 PTIS3 Unaffected by reset Figure 2-21. Port S Input Register (PTIS) Table 2-20. PTIS Register Field Descriptions Description Access: User read PTIS2 PTIS1 Freescale Semiconductor 1 0 PTIS0 u ...
Page 87
... If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction Else If IIC is routing to PS and IIC is enabled, it will force as open-drain output Else if PWM0 is routing to PS and PWM0 is enabled it will force as output. 1 Associated pin is configured as output. 0 Associated pin is configured as input. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor DDRS5 DDRS4 ...
Page 88
... Port S Reduced Drive Register (RDRS) Address 0x024B RDRS7 RDRS6 W Reset 0 0 Figure 2-23. Port S Reduced Drive Register (RDRS) 1 Read: Anytime. Write: Anytime. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 88 Description NOTE RDRS5 RDRS4 RDRS3 Access: User read/write RDRS2 RDRS1 RDRS0 Freescale Semiconductor 1 ...
Page 89
... Address 0x024D PPSS7 PPSS6 W Reset 0 0 Figure 2-25. Port S Polarity Select Register (PPSS) 1 Read: Anytime. Write: Anytime. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Description 5 4 PERS5 PERS4 PERS3 1 1 Table 2-23. PERS Register Field Descriptions Description 5 4 PPSS5 PPSS4 PPSS3 ...
Page 90
... This register configures the re-routing of IIC and SPI on alternative ports. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 90 Table 2-24. PPSS Register Field Descriptions Description 5 4 WOMS5 WOMS4 WOMS3 0 0 Description 5 4 PTSRR5 PTSRR4 0 0 Access: User read/write WOMS2 WOMS1 Access: User read/write PTSRR1 Freescale Semiconductor 1 0 WOMS0 PTSRR0 0 ...
Page 91
... Read: Always reads 0x00 Write: Unimplemented 2.3.31 Port P Data Register (PTP) Address 0x0258 PTP7 PTP6 W PWM7 PWM6 Altern. FP7 FP6 Function Reset 0 0 MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Table 2-26. Module Routing Summary PTSRR Related Pins SCL PS4 PH0 PR6 x ...
Page 92
... Table 2-27. PTP Register Field Descriptions Description 5 4 PTIP5 PTIP4 PTIP3 Unaffected by reset Figure 2-30. Port P Input Register (PTIP) Table 2-28. PTIP Register Field Descriptions Description 5 4 DDRP5 DDRP4 DDRP3 0 0 Access: User read PTIP2 PTIP1 Access: User read/write DDRP2 DDRP1 Freescale Semiconductor 1 0 PTIP0 DDRP0 0 ...
Page 93
... This register configures the drive strength of output pins 7 through 0 as either full or reduced pin is used as input this bit has no effect. 1 Reduced drive selected (1/6 of the full drive strength). 0 Full drive strength enabled. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Description NOTE 5 4 ...
Page 94
... MC9S12HY/HA-Family Reference Manual, Rev. 1. PERP5 PERP4 PERP3 1 1 Table 2-31. PERP Register Field Descriptions Description 5 4 PPSP5 PPSP4 PPSP3 1 1 Table 2-32. PPSP Register Field Descriptions Description Access: User read/write PERP2 PERP1 Access: User read/write PPSP2 PPSP1 Freescale Semiconductor 1 0 PERP0 PPSP0 1 ...
Page 95
... Table 2-34. PTPRRL Register Field Descriptions Field 7-0 Port P Routing Register Low— PTPRRL The register decide the PWM channel routing on the Port S/P/V The PTPRRH/PTPRRL register configures the re-routing of PWM on alternative ports. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Description ...
Page 96
... FP23 FP22 0 0 Figure 2-37. Port H Data Register (PTH) Related Pins PP5 PV1 PP4 PV0 PP3 PS7 PP2 PS6 PP1 PS5 Access: User read/write PTH2 PTH1 ECLK — SCK MOSI FP21 FP20 Freescale Semiconductor PP0 PS4 1 0 PTH0 2 MISO SCL FP19 0 ...
Page 97
... The SCL of IIC takes precedence over the SPI and the general purpose I/O function • The MISO of SPI takes precedence over the general purpose I/O function MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Table 2-36. PTH Register Field Descriptions Description ...
Page 98
... MC9S12HY/HA-Family Reference Manual, Rev. 1. PTIH5 PTIH4 PTIH3 Unaffected by reset Figure 2-38. Port H Input Register (PTIH) Table 2-37. PTIH Register Field Descriptions Description 5 4 DDRH5 DDRH4 DDRH3 0 0 Access: User read PTIH2 PTIH1 Access: User read/write DDRH2 DDRH1 Freescale Semiconductor 1 0 PTIH0 DDRH0 0 ...
Page 99
... Associated pin is configured as output. 0 Associated pin is configured as input. Due to internal synchronization circuits, it can take bus clock cycles until the correct value is read on PTH or PTIH registers, when changing the DDRH register. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Port Integration Module (S12HYPIMV1) Description NOTE 99 ...
Page 100
... Pull device disabled. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 100 5 4 RDRH5 RDRH4 RDRH3 0 0 Description 5 4 PERH5 PERH4 PERH3 1 1 Table 2-40. PERH Register Field Descriptions Description Access: User read/write RDRH2 RDRH1 Access: User read/write PERH2 PERH1 Freescale Semiconductor 1 0 RDRH0 PERH0 1 ...
Page 101
... These bits have no influence on pins used as inputs. 1 Output buffers operate as open-drain outputs. 0 Output buffers operate as push-pull outputs. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 5 4 PPSH5 PPSH4 PPSH3 ...
Page 102
... Reset Unimplemented or Reserved 1 Read: Always reads 0x00 Write: Unimplemented MC9S12HY/HA-Family Reference Manual, Rev. 1.04 102 Figure 2-44. PIM Reserved Register Figure 2-45. PIM Reserved Register Figure 2-46. PIM Reserved Register 1 Access: User read Access: User read Access: User read Freescale Semiconductor ...
Page 103
... PIM Reserved Register Address 0x0272 Reset Unimplemented or Reserved 1 Read: Always reads 0x00 Write: Unimplemented MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 5 4 PT1AD5 PT1AD4 PT1AD3 KWAD5 KWAD4 KWAD3 AN5 AN4 AN3 0 0 Figure 2-47. Port AD Data Register (PT1AD) Description 5 4 ...
Page 104
... PIM Reserved Register Address 0x0274 Reset Unimplemented or Reserved 1 Read: Always reads 0x00 Write: Unimplemented MC9S12HY/HA-Family Reference Manual, Rev. 1.04 104 DDR1AD5 DDR1AD4 DDR1AD3 Description NOTE Figure 2-50. PIM Reserved Register Access: User read/write DDR1AD2 DDR1AD1 DDR1AD0 Access: User read Freescale Semiconductor 1 1 ...
Page 105
... Unimplemented or Reserved 1 Read: Always reads 0x00 Write: Unimplemented 2.3.55 Port AD Pull Up Enable Register (PER1AD) Address 0x0277 PER1AD7 PER1AD6 W Reset 0 0 Figure 2-53. Port AD Pull Up Enable Register (PER1AD) MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor RDR1AD5 RDR1AD4 RDR1AD3 Description Figure 2-52. PIM Reserved Register ...
Page 106
... Description Unaffected by reset Figure 2-54. PIM Reserved Registers PTR5 PTR4 PTR3 SDA — — FP17 FP112 IOC1_7 Figure 2-55. Port R Data Register (PTR) Access: User read Access: User read/write PTR2 PTR1 PTR0 — — — IOC1_6 IOC0_7 IOC0_6 Freescale Semiconductor 1 1 ...
Page 107
... The TIM1/TIM0 output compare function takes precedence over the general purpose I/O function 1 In order TIM input capture to be function correctly, the corresponding DDRR bit should be set as input state MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Table 2-47. PTR Register Field Descriptions Description Port Integration Module (S12HYPIMV1) ...
Page 108
... MC9S12HY/HA-Family Reference Manual, Rev. 1.04 108 5 4 PTIR5 PTIR4 PTIR3 Unaffected by reset Figure 2-56. Port R Input Register (PTIR) Table 2-48. PTIR Register Field Descriptions Description 5 4 DDRR5 DDRR4 DDRR3 0 0 Access: User read PTIR2 PTIR1 Access: User read/write DDRR2 DDRR1 Freescale Semiconductor 1 0 PTIR0 DDRR0 0 ...
Page 109
... Associated pin is configured as input. Due to internal synchronization circuits, it can take bus clock cycles until the correct value is read on PTR or PTIR registers, when changing the DDRR register. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Port Integration Module (S12HYPIMV1) Description NOTE 109 ...
Page 110
... Pull device disabled. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 110 5 4 RDRR5 RDRR4 RDRR3 0 0 Description 5 4 PERR5 PERR4 PERR3 1 1 Table 2-51. PERR Register Field Descriptions Description Access: User read/write RDRR2 RDRR1 Access: User read/write PERR2 PERR1 Freescale Semiconductor 1 0 RDRR0 PERR0 1 ...
Page 111
... These bits have no influence on pins used as inputs. 1 Output buffers operate as open-drain outputs. 0 Output buffers operate as push-pull outputs. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 5 4 PPSR5 PPSR4 PPSR3 ...
Page 112
... Unaffected by reset Figure 2-62. PIM Reserved Registers 5 4 PIET5 PIET4 PIET3 0 0 Table 2-54. PIET Register Field Descriptions Description 5 4 PIFT5 PIFT4 PIFT3 0 0 Access: User read Access: User read/write PIET2 PIET1 Access: User read/write PIFT2 PIFT1 Freescale Semiconductor PIET0 PIFT0 0 ...
Page 113
... Port S Interrupt Flag Register (PIFS) Address 0x028B PIFS6 W Reset 0 0 Figure 2-66. Port S Interrupt Flag Register (PIFS) 1 Read: Anytime. Write: Anytime. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Table 2-55. PIFT Register Field Descriptions Description PIES5 0 0 Table 2-56. PIES Register Field Descriptions Description PIFS5 0 ...
Page 114
... Write: Anytime. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 114 Table 2-57. PIFS Register Field Descriptions Description 5 4 PIE1AD5 PIE1AD4 PIE1AD3 0 0 Description 5 4 PIF1AD5 PIF1AD4 PIF1AD3 0 0 Access: User read/write PIE1AD2 PIE1AD1 Access: User read/write PIF1AD2 PIF1AD1 Freescale Semiconductor 1 0 PIE1AD0 PIF1AD0 0 ...
Page 115
... Interrupt is disabled (interrupt flag masked). 2.3.72 Port R Interrupt Flag Register (PIFR) Address 0x028F Reset 0 0 Figure 2-70. Port R Interrupt Flag Register (PIFR) 1 Read: Anytime. Write: Anytime. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Description PIER3 0 0 Table 2-60. PIER Register Field Descriptions Description PIFR3 0 0 ...
Page 116
... Table 2-61. PIFR Register Field Descriptions Description 5 4 PTU5 PTU4 PTU3 — IOC0_2 M1C0P M1C0M M0C1P 0 0 Figure 2-71. Port U Data Register (PTU) Table 2-62. PTU Register Field Descriptions Description Access: User read/write PTU2 PTU1 — IOC0_1 — M0C1M M0C0P Freescale Semiconductor 1 0 PTU0 IOC0_0 M0C0M 0 1 ...
Page 117
... If enabled the Motor driver PWM output it will force the I/O state to be output. Else if corresponding TIM0 output compare channel is enabled, it will be force as output 1 Associated pin is configured as output. 0 Associated pin is configured as input. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 5 4 PTIU5 PTIU4 ...
Page 118
... Pull device enabled. 0 Pull device disabled. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 118 NOTE Unaffected by reset Figure 2-74. PIM Reserved Registers 5 4 PERU5 PERU4 PERU3 0 0 Table 2-65. PERU Register Field Descriptions Description Access: User read Access: User read/write PERU2 PERU1 Freescale Semiconductor PERU0 0 ...
Page 119
... When enter STOP, to save the power, the slew rate control will be force to off state. After wakeup from STOP, it will also need to wait about 300 nanoseconds before slew rate control to be function as setting. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 5 4 ...
Page 120
... Port Integration Module (S12HYPIMV1) 2.3.80 PIM Reserved Registers Address 0x0297 Reset Unimplemented or Reserved 1 Read: Always reads 0x00 Write: Unimplemented MC9S12HY/HA-Family Reference Manual, Rev. 1.04 120 Unaffected by reset Figure 2-78. PIM Reserved Registers 1 Access: User read Freescale Semiconductor ...
Page 121
... The Motor driver PWM takes precedence over the TIM1 and the general purpose I/O function. • The TIM1 output compare function takes precedence over the general purpose I/O function if the related channels 1 is enabled MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 5 4 PTV5 PTV4 PTV3 — ...
Page 122
... In order TIM1 input capture to be function correctly, need to disable all the output functions on the corresponding channel. Also the corresponding SRRV bit should be set to 0. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 122 Table 2-68. PTV register Field Descriptions Description 1 1 Freescale Semiconductor ...
Page 123
... DDRV7 DDRV6 W Reset 0 0 Figure 2-81. Port V Data Direction Register (DDRV) 1 Read: Anytime. Write: Anytime. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 5 4 PTIV5 PTIV4 PTIV3 Unaffected by reset Figure 2-80. Port V Input Register (PTIV) Table 2-69. PTIV Register Field Descriptions Description ...
Page 124
... Else if SPI is routing to PV and SPI is enabled, SPI will determined the I/O state Else if PWM6 is routing to PV, it will force the I/O state to be output. 1 Associated pin is configured as output. 0 Associated pin is configured as input. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 124 Description Freescale Semiconductor ...
Page 125
... PTV or PTIV registers, when changing the DDRV register. 2.3.84 PIM Reserved Registers Address 0x029B Reset Unimplemented or Reserved 1 Read: Always reads 0x00 Write: Unimplemented MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Description NOTE Unaffected by reset Figure 2-82. PIM Reserved Registers Port Integration Module (S12HYPIMV1) 1 Access: User read 2 1 ...
Page 126
... MC9S12HY/HA-Family Reference Manual, Rev. 1.04 126 5 4 PERV5 PERV4 PERV3 0 0 Table 2-71. PERV Register Field Descriptions Description 5 4 PPSV5 PPSV4 PPSV3 0 0 Table 2-72. PPSV Register Field Descriptions Description Access: User read/write PERV2 PERV1 Access: User read/write PPSV2 PPSV1 Freescale Semiconductor 1 0 PERV0 PPSV0 0 ...
Page 127
... Write: Unimplemented 2.4 Functional Description 2.4.1 General Each pin except BKGD can act as general purpose I/O. In addition each pin can act as an output or input of a peripheral module. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 5 4 SRRV5 SRRV4 SRRV3 0 0 Table 2-73. SRRV Register Field Descriptions ...
Page 128
... MC9S12HY/HA-Family Reference Manual, Rev. 1.04 (Table 1 Wired- Slew Interrupt Interrupt Or Mode Rate Enable - - - - - - - - yes yes - yes yes - yes - - - yes - - - - yes - yes - - yes - (Figure 2-87). (Figure Freescale Semiconductor 2-74). All Routing Flag - - - - yes yes yes yes yes yes - yes - - yes - - - - - 2-87). ...
Page 129
... Polarity select register (PPSx) This register selects either a pull-up or pull-down device if enabled. It becomes only active if the pin is used as an input. A pull-up device can be activated if the pin is used as a wired-or output. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor NOTE PTI ...
Page 130
... During reset, the BKGD pin is used as MODC input. 2.4.3.2 Port AD This port is associated with the ATD. 2.4.3.3 Port A, B These ports are associated with LCD, IRQ, XIRQ and API_EXTCLK 2.4.3.4 Port H This port is associated with LCD/SPI/IIC. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 130 NOTE Freescale Semiconductor ...
Page 131
... A digital filter on each pin prevents pulses interrupt. The minimum time varies over process conditions, temperature and voltage Table 2-75). MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor (Figure 2-89) shorter than a specified time from generating an Port Integration Module (S12HYPIMV1) (Figure 2-88 ...
Page 132
... Table 2-75. Pulse Detection Criteria Mode STOP Unit t 3 bus clocks pulse 3 < t < 4 bus clocks pulse t 4 bus clocks pulse t pulse Figure 2-89. Pulse Illustration 1 STOP t t pulse pign t < t < t pign pulse pval t t pulse pval Freescale Semiconductor ...
Page 133
... It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Port Integration Module (S12HYPIMV1) 133 ...
Page 134
... Port Integration Module (S12HYPIMV1) MC9S12HY/HA-Family Reference Manual, Rev. 1.04 134 Freescale Semiconductor ...
Page 135
... Unimplemented Address Ranges Address ranges which are not mapped to any on-chip ressource. P-Flash D-Plash NVM IFR MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Table 3-1. Revision History Table Substantial Change(s) Corrected the address offset of the PPAGE register Removed “Table 1-9. MC9S12P Derivatives” Map” ...
Page 136
... S12P devives can be secured to prohibit external access to the on-chip P-Flash. The S12PMMC module determines the access permissions to the on-chip memories in secured and unsecured state. 3.1.5 Block Diagram Figure 3-1 shows a block diagram of the S12PMMC. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 136 Freescale Semiconductor ...
Page 137
... Module Memory Map A summary of the registers associated with the S12PMMC block is shown in descriptions of the registers and bits are given in the subsections that follow. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Address Decoder & Priority Target Bus Controller P-Flash RAM Figure 3-1. S12PMMC Block Diagram The RESET pin is used the select the MCU’ ...
Page 138
... DP12 Unimplemented or Reserved Figure 3-2. MMC Register Summary Figure 3-3. Mode Register (MODE) Figure 3-4). Table 3-4. MODE Field Descriptions Description DP11 DP10 DP9 PIX3 PIX2 PIX1 Figure 3-4). Figure 3-4 illustrates all allowed mode Freescale Semiconductor Bit 0 0 DP8 PIX0 ...
Page 139
... Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct DP[15:8] addressing mode. These register bits form bits [15:8] of the local address (see Bit17 Bit16 MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor RESET ...
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... PIX3 Global Address [17:0] Bit14 Bit13 Address [13:0] Address: CPU Local Address Figure 3-8. PPAGE Address Mapping NOTE 2 1 PIX2 PIX1 1 1 Figure 3-8). This supports accessing Bit0 or BDM Local Address Freescale Semiconductor 0 PIX0 0 ...
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... CPU begins execution of firmware commands or the BDM begins execution of hardware commands. The resources which share memory space with the BDM module will not be visible in the memory map during active BDM mode. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Table 3-6. PPAGE Field Descriptions Description S12P Memory Map Control (S12PMMCV1) ...
Page 142
... The BDM program page index register (BDMPPR) is used only when the feature is enabled in BDM and, in the case the CPU is executing a firmware command which uses CPU instructions BDM hardware commands. See the BDM Block Guide for further details. (see MC9S12HY/HA-Family Reference Manual, Rev. 1.04 142 Instructions). Figure 3-9). Freescale Semiconductor ...
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... Bit17 BDMPPR Register [3:0] Bit17 BDMPPR Register [3:0] MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor BDM HARDWARE COMMAND Global Address [17:0] Bit14 Bit13 BDM Local Address [13:0] BDM FIRMWARE COMMAND Global Address [17:0] Bit13 Bit14 CPU Local Address [13:0] Figure 3-9. BDMPPR Address Mapping ...
Page 144
... MC9S12HY/HA-Family Reference Manual, Rev. 1.04 144 0x0_0000 RAM_LOW 0x0_4000 0x0_4400 0x0_5400 0x0_8000 0x3_0000 PPAGE 0x3_4000 0x3_8000 0x3_C000 0x3_FFFF Global Memory Map REGISTERS Unimplemented Area RAM NVM Resources D-Flash NVM Resources P-Flash 10 *16K paged Unpaged P-Flash Unpaged P-Flash Unpaged P-Flash Unpaged P-Flash Freescale Semiconductor ...
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... No misaligned word access from the BDM module will occur; these accesses are blocked in the BDM module (Refer to BDM Block Guide). MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Bottom Address 0x0_0000 RAM_LOW = ...
Page 146
... Unpaged P-Flash 0xFFFF Figure 3-11. Implemented Global Address Mapping MC9S12HY/HA-Family Reference Manual, Rev. 1.04 146 0x0_0000 RAM_LOW 0x0_4000 0x0_4400 0x0_5400 0x0_8000 PPAGE PF_LOW 0x3_FFFF Global Memory Map REGISTERS Unimplemented Area RAM NVM Resources D-Flash NVM Resources Unimplemented area P-Flash Freescale Semiconductor ...
Page 147
... CPU will be stalled after finishing the current operation and the BDM will gain access to the bus. 3.5.3 Interrupts The MMC does not generate any interrupts MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor CPU S12X0 MMC “Crossbar Switch” XBUS0 BDM ...
Page 148
... This sequence is uninterruptable. The RTC can be executed from anywhere in the local CPU memory space. The CALL and RTC instructions behave like JSR and RTS instruction, they however require more execution cycles. Usage of JSR/RTS instructions is therefore recommended when possible and MC9S12HY/HA-Family Reference Manual, Rev. 1.04 148 Freescale Semiconductor ...
Page 149
... RTC instruction must be called using the CALL instruction even when the correct page is already present in the memory map. This is to make sure that the correct PPAGE value will be present on stack at the time of the RTC instruction execution. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor S12P Memory Map Control (S12PMMCV1) 149 ...
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... S12P Memory Map Control (S12PMMCV1) MC9S12HY/HA-Family Reference Manual, Rev. 1.04 150 Freescale Semiconductor ...
Page 151
... Interrupt vector base register (IVBR) • One spurious interrupt vector (at address vector base MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Author removed references to XIRQ/IRQ and added D2D error and D2D interrupt instead updates for S12P family devices: - re-added XIRQ and IRQ references since this functionality is used ...
Page 152
... The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as upper byte) and 0x00 (used as lower byte). MC9S12HY/HA-Family Reference Manual, Rev. 1.04 152 for details. for details. Section 4.5.3, “Wake Up Section 4.5.3, “Wake Up for details. Freescale Semiconductor ...
Page 153
... Interrupt Vector Base Register (IVBR) Address: 0x0120 Reset 1 1 Figure 4-2. Interrupt Vector Base Register (IVBR) Read: Anytime Write: Anytime MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Interrupt Requests Figure 4-1. INT Block Diagram IVB_ADDR[7: Interrupt Module (S12SINTV1) Wake Up CPU ...
Page 154
... In this case, the CPU will receive the highest priority vector and the system will process this interrupt request first, before the original interrupt request is processed. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 154 Table 4-3. IVBR Field Descriptions Description NOTE Freescale Semiconductor ...
Page 155
... D2D error interrupt on MCUs featuring a D2D initiator module, otherwise XIRQ pin interrupt 3 D2D interrupt on MCUs featuring a D2D initiator module, otherwise IRQ pin interrupt MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor NOTE Table 4-4. 3 Interrupt Module (S12SINTV1) Source ...
Page 156
... X bit in CCR is set. If the X bit maskable interrupt request is used to wake-up the MCU with the X bit in the CCR set, the associated ISR is not called. The CPU then resumes program execution with the instruction following the MC9S12HY/HA-Family Reference Manual, Rev. 1.04 156 Freescale Semiconductor ...
Page 157
... WAI or STOP instruction. This features works the same rules like any interrupt request, i.e. care must be taken that the X interrupt request used for wake-up remains active at least until the system begins execution of the instruction following the WAI or STOP instruction; otherwise, wake-up may not occur. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Interrupt Module (S12SINTV1) 157 ...
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... Interrupt Module (S12SINTV1) MC9S12HY/HA-Family Reference Manual, Rev. 1.04 158 Freescale Semiconductor ...
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... Clock switch removed from BDM (CLKSW bit removed from BDMSTS register) 5.1.1 Features The BDM includes these distinctive features: MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Summary of Changes First version of S12SBDMV1 Updated register address information & Block Version Removed CLKSW bit and description ...
Page 160
... If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure operation prevents access to Flash other than allowing erasure. For more information please see Section 5.4.1, MC9S12HY/HA-Family Reference Manual, Rev. 1.04 160 “Security”. Freescale Semiconductor ...
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... Serial System BKGD Interface Register Block TRACE BDMACT ENBDM SDV UNSEC BDMSTS Register MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Figure 5-1. Data 16-Bit Shift Register Control Instruction Code and Execution Standard BDM Firmware LOOKUP TABLE Secured BDM Firmware LOOKUP TABLE Figure 5-1 ...
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... BDM memory map when BDM is active. Global Address 0x3_FF00–0x3_FF0B 0x3_FF0C–0x3_FF0E 0x3_FF0F 0x3_FF10–0x3_FFFF MC9S12HY/HA-Family Reference Manual, Rev. 1.04 162 Table 5-1. BDM Memory Map Module BDM registers BDM firmware ROM Family ID (part of BDM firmware ROM) BDM firmware ROM Size (Bytes 240 Freescale Semiconductor ...
Page 163
... X W 0x3_FF04 Reserved 0x3_FF05 Reserved 0x3_FF06 BDMCCR R CCR7 W 0x3_FF07 Reserved 0x3_FF08 BDMPPR R BPAE W 0x3_FF09 Reserved 0x3_FF0A Reserved 0x3_FF0B Reserved MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Figure BDMACT 0 SDV CCR6 CCR5 CCR4 Unimplemented, Reserved = Indeterminate Figure 5-2. BDM Register Summary Background Debug Module (S12SBDMV1) 5-2 ...
Page 164
... BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from the map. 0 BDM not active 1 BDM active MC9S12HY/HA-Family Reference Manual, Rev. 1.04 164 BDMACT 0 SDV Unimplemented, Reserved = Always read zero Figure 5-3. BDM Status Register (BDMSTS) Table 5-2. BDMSTS Field Descriptions Description TRACE 0 UNSEC Implemented (do not alter) Freescale Semiconductor ...
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... BDMCCR register. However, out of special single-chip reset, the BDMCCR is set to 0xD8 and not 0xD0 which is the reset value of the CCR register in this CPU mode. Out of reset in all other modes the BDMCCR register is read zero. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Description ...
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... Section 5.4.3, “BDM Hardware MC9S12HY/HA-Family Reference Manual, Rev. 1.04 166 BPP3 Table 5-3. BDMPPR Field Descriptions Description Commands”. Target system memory Commands”. The CPU resources referred to are the Commands”) and in secure mode (see BPP2 BPP1 BPP0 Section 5.4.1, Freescale Semiconductor ...
Page 167
... BDM. However, these registers are not readable by user programs. 1. BDM is enabled and active immediately out of special single-chip reset. 2. This method is provided by the S12S_DBG module. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Background Debug Module (S12SBDMV1 ...
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... Odd address data on low byte; even address data on high byte. Read from memory with standard BDM firmware lookup table out of map. Must be aligned access. Write to memory with standard BDM firmware lookup table in map. Odd address data on low byte; even address data on high byte. Description Freescale Semiconductor ...
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... BDM firmware. The standard BDM firmware watches for serial commands and executes them as they are received. The firmware commands are shown in MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Table 5-4. Hardware Commands (continued) Data Write to memory with standard BDM firmware lookup table in map. ...
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... ACK will occur upon returning to active background mode. none (Previous enable tagging and go to user program.) This command will be deprecated and should not be used anymore. Opcode will be executed command. Section 5.4.7, “Serial Interface Hardware Handshake Protocol” Description last note). Freescale Semiconductor ...
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... For firmware write commands, the external host must wait 36 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Background Debug Module (S12SBDMV1) 171 ...
Page 172
... Next Data Command Next Command Figure 5-6. BDM Command Structure for information on how serial clock rate is selected Bits AT ~16 TC/Bit Next Data Command 150-BC Delay Next Command BC = Bus Clock Cycles TC = Target Clock Cycles Section 5.4.6, “BDM Serial Interface” Freescale Semiconductor ...
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... Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Background Debug Module (S12SBDMV1) Figure 5-7 and that of target-to-host in Figure 5-8 ...
Page 174
... Figure 5-8. BDM Target-to-Host Serial Bit Timing (Logic 1) MC9S12HY/HA-Family Reference Manual, Rev. 1.04 174 Target Senses Bit 10 Cycles Figure 5-8 shows the host receiving a logic 1 from the target High-Impedance R-C Rise 10 Cycles 10 Cycles Host Samples BKGD Pin Earliest Start of Next Bit High-Impedance Earliest Start of Next Bit Freescale Semiconductor ...
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... ACK pulse, since the command execution depends upon the CPU bus, which in some cases could be very slow due to long MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor High-Impedance 10 Cycles ...
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... Speedup Pulse Minimum Delay From the BDM Command NOTE Target BDM Executes the BDM Decodes READ_BYTE Command the Command High-Impedance Earliest Start of Next Bit Host (2) Bytes are New BDM Retrieved Command Host Target BDM Issues the ACK Pulse (out of scale) Freescale Semiconductor ...
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... ACK pulse will be aborted. A pending GO, TRACE1 or GO_UNTIL command can not be aborted. Only the corresponding ACK pulse can be aborted by the SYNC command. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor specifies the timing when the BKGD pin is being driven, so the host NOTE NOTE Pulse” ...
Page 178
... BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this MC9S12HY/HA-Family Reference Manual, Rev. 1.04 178 NOTE SYNC Response From the Target (Out of Scale) (Out of Scale) READ_STATUS Host BDM Decode NOTE Section 5.4.9, “SYNC — Request New BDM Command Target Host Target New BDM Command Freescale Semiconductor ...
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... The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if the target supports the hardware handshake protocol ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor At Least 128 Cycles ACK Pulse High-Impedance Electrical Confl ...
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... The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 180 Freescale Semiconductor ...
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... ACK pulse. The handshake feature becomes disabled only when system stop mode has been reached. Hence after a system stop mode the handshake feature must be enabled again by sending the ACK_ENABLE command. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Background Debug Module (S12SBDMV1) 181 ...
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... The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 182 Freescale Semiconductor ...
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... DBG: S12SDBG module POR: Power On Reset MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Table 6-1. Revision History Sections Summary of Changes Affected 6.5 Added application information General Spelling corrections. Revision history format changed. 6.4.5.4 Added note for end aligned, PurePC, rollover case. Freescale Semiconductor ...
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... Detail: address and data for all cycles except free cycles and opcode fetches are stored — Compressed Pure PC: all program counter addresses are stored • 4-stage state sequencer for trace buffer control — Tracing session trigger linked to Final State of state sequencer MC9S12HY/HA-Family Reference Manual, Rev. 1.04 184 Freescale Semiconductor ...
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... COMPARATOR A CPU BUS COMPARATOR B COMPARATOR C READ TRACE DATA (DBG READ DATA BUS) 6.2 External Signal Description There are no external signals associated with this module. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Comparator Breakpoints Matches Enabled Possible Yes Yes Yes Only SWI ...
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... SSF1 0 TRCMOD 0 0 ABCM Bit 11 Bit 10 Bit 9 Bit 3 Bit 2 Bit 1 CNT SC3 SC2 SC1 0 MC2 MC1 RW RWE NDB 0 RW RWE 0 RW RWE 0 0 Bit Freescale Semiconductor Bit 0 SSF0 TALIGN Bit 8 Bit 0 SC0 MC0 COMPE COMPE COMPE Bit 16 Bit 8 Bit 0 Bit 8 Bit 0 ...
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... When disarming the DBG by clearing ARM with software, the contents of bits[4:3] are not affected by the write, since up until the write operation, ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor ...
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... MC9S12HY/HA-Family Reference Manual, Rev. 1.04 188 Table 6-3. DBGC1 Field Descriptions Description Table 6-4. COMRV Encoding Visible Comparator Visible Register at 0x0027 Comparator A Comparator B Comparator C None Figure 6-4. Debug Status Register (DBGSR) Table 6-4. DBGSCR1 DBGSCR2 DBGSCR3 DBGMFR SSF2 SSF1 Freescale Semiconductor 0 SSF0 0 0 ...
Page 189
... On arming the module the state sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 6-6. SSF[2:0] — State Sequence Flag Bit Encoding 101,110,111 MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor Table 6-5. DBGSR Field Descriptions Description SSF[2:0] Current State ...
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... Table 6-8. TRCMOD Trace Mode Bit Encoding TRCMOD MC9S12HY/HA-Family Reference Manual, Rev. 1.04 190 Table 6-7. DBGTCR Field Descriptions Description 6.4.5.2 for detailed Trace Mode descriptions. In Normal Mode, change of flow Description Normal Loop1 Detail Compressed Pure TRCMOD 0 0 Table Freescale Semiconductor 0 TALIGN 0 6-8. ...
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... Figure 6-7. Debug Trace Buffer Register (DBGTB) Read: Only when unlocked AND unsecured AND not armed AND TSOURCE set. Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor ...
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... Similarly reads while the debugger is armed or with the TSOURCE bit clear, return 0 and do not affect the trace buffer pointer. The POR state is undefined. Other resets do not affect the trace buffer contents. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 192 Table 6-11. DBGTB Field Descriptions Description Freescale Semiconductor ...
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... MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor 5 4 — — — Table 6-12. DBGCNT Field Descriptions Description Table 6-13. CNT Decoding Table .. 64 lines valid; if using Begin trigger alignment, ARM bit will be cleared and the tracing session ends. ...
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... Each register can be accessed using the COMRV bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register (DBGMFR). Table 6-14. State Control Register Access Encoding COMRV MC9S12HY/HA-Family Reference Manual, Rev. 1.04 194 Visible State Control Register 00 DBGSCR1 01 DBGSCR2 10 DBGSCR3 11 DBGMFR Freescale Semiconductor ...
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... The priorities described in Table 6-36 final state has priority followed by the match on the lower channel number (0,1,2). Thus with SC[3:0]=1101 a simultaneous match0/match1 transitions to final state. MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor SC3 and described in 6.3.2.8.1. Comparators must be enabled by setting Table 6-15 ...
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... Match2 to State1..... Match0 to Final State Either Match0 or Match1 to Final State Reserved Reserved Reserved Reserved Either Match0 or Match1 to Final State........Match2 to State3 Reserved Reserved Either Match0 or Match1 to Final State........Match2 to State1 dictate that in the case of simultaneous matches, a match leading SC2 SC1 SC0 Freescale Semiconductor ...
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... The priorities described in Table 6-36 final state has priority followed by the match on the lower channel number (0,1,2). MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor SC3 and described in 6.3.2.8.1. Comparators must be enabled by setting Table 6-19. DBGSCR3 Field Descriptions Description Description (Unspecifi ...
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... MC9S12HY/HA-Family Reference Manual, Rev. 1.04 198 Table 6-21. Comparator Register Layout Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write MC2 MC1 MC0 Comparators A,B and C Comparators A,B and C Comparators A,B and C Comparators A,B and C Comparator A only Comparator A only Comparator A only Comparator A only Freescale Semiconductor ...
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... Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the SZ associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set. (Comparators 0 Word access size is compared A and B) 1 Byte access size is compared MC9S12HY/HA-Family Reference Manual, Rev. 1.04 Freescale Semiconductor TAG BRK RW 0 ...
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... TAG bit is set since the match occurs based on the tagged opcode reaching the execution stage of the instruction queue. Table 6-23. Read or Write Comparison Logic Table RWE Bit RW Bit MC9S12HY/HA-Family Reference Manual, Rev. 1.04 200 Description RW Signal not used in comparison not used in comparison Comment Write data bus No match No match Read data bus Freescale Semiconductor ...