S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 246

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.3.2.9
This register controls the COP (Computer Operating Properly) watchdog.
The clock source for the COP is either IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL=1 and PCE=1 the COP
continues to run, else the COP counter halts in Stop Mode.
Read: Anytime
Write:
When a non-zero value is loaded from Flash to CR[2:0] the COP time-out period is started.
A change of the COPOSCSEL bit (writing a different value or loosing UPOSC status) re-starts the COP
time-out period.
In normal mode the COP time-out period is restarted if either of these conditions is true:
In special mode, any write access to CPMUCOP register restarts the COP time-out period.
246
0x003C
After de-assert of System Reset the values are automatically loaded from the Flash memory. See Device specification for
Reset
1. RSBCK: anytime in special mode; write to “1” but not to “0” in normal mode
2. WCOP, CR2, CR1, CR0:
1. Writing a non-zero value to CR[2:0] (anytime in special mode, once in normal mode) with
2. Writing WCOP bit (anytime in special mode, once in normal mode) with WRTMASK = 0.
3. Changing RSBCK bit from “0” to “1”.
details.
W
R
— Anytime in special mode, when WRTMASK is 0, otherwise it has no effect
— Write once in normal mode, when WRTMASK is 0, otherwise it has no effect.
WRTMASK = 0.
– Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.
– Writing WCOP to “0” has no effect, but counts for the “write once” condition.
WCOP
S12CPMU COP Control Register (CPMUCOP)
F
7
= Unimplemented or Reserved
RSBCK
Figure 7-12. S12CPMU COP Control Register (CPMUCOP)
0
6
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
WRTMASK
0
0
5
0
0
4
0
0
3
CR2
F
2
Freescale Semiconductor
CR1
F
1
CR0
F
0