S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 111

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
1
2.3.62
2.3.63
Freescale Semiconductor
Address 0x0285
Address 0x0286
WOMR
Read: Anytime.
Write: Anytime.
Read: Anytime.
Write: Anytime.
PPSR
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
Port R pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin. The 3-0 bits also select the
polarity of the active interrupt edge
1 A rising edge on the associated Port R pin sets the associated flag bit in the PIFR register. A pull-down device is
0 A falling edge on the associated Port R pin sets the associated flag bit in the PIFR register. A pull-up device is
Port R wired-or mode—Enable wired-or functionality
This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain). A
logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no
influence on pins used as inputs.
1 Output buffers operate as open-drain outputs.
0 Output buffers operate as push-pull outputs.
WOMR7
PPSR7
Port R Polarity Select Register (PPSR)
Port R Wired-Or Mode Register (WOMR)
connected to the associated pin, if enabled and if the pin is used as input.
connected to the associated pin, if enabled and if the pin is used as input.
1
0
7
7
WOMR6
PPSR6
1
0
6
6
Figure 2-61. Port R Wired-Or Mode Register (WOMR)
Figure 2-60. Port R Polarity Select Register (PPSR)
Table 2-53. WOMR Register Field Descriptions
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-52. PPSR Register Field Descriptions
WOMR5
PPSR5
1
0
5
5
WOMR4
PPSR4
1
0
4
4
Description
Description
WOMR3
PPSR3
3
1
3
0
WOMR2
PPSR2
Port Integration Module (S12HYPIMV1)
1
0
2
2
WOMR1
PPSR1
Access: User read/write
Access: User read/write
1
0
1
1
WOMR0
PPSR0
1
0
0
0
111
1
1