S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 174

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Background Debug Module (S12SBDMV1)
The receive cases are more complicated.
system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the
host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the
BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the
perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it
started the bit time.
174
Start of Bit Time
Start of Bit Time
Target System
(Target MCU)
(Target MCU)
BDM Clock
BDM Clock
BKGD Pin
BKGD Pin
Transmit 1
Transmit 0
Perceived
Perceived
Speedup
Drive to
Pulse
Host
Host
Host
Synchronization
Uncertainty
Figure 5-8. BDM Target-to-Host Serial Bit Timing (Logic 1)
High-Impedance
Figure 5-7. BDM Host-to-Target Serial Bit Timing
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
10 Cycles
R-C Rise
Figure 5-8
10 Cycles
10 Cycles
shows the host receiving a logic 1 from the target
Target Senses Bit
Host Samples
High-Impedance
BKGD Pin
High-Impedance
Freescale Semiconductor
Next Bit
Earliest
Start of
Next Bit
Earliest
Start of