S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 485

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 14
Timer Module (TIM16B8CV2) Block Description
14.1
The basic timer consists of a 16-bit, software-programmable counter driven by a enhanced programmable
prescaler.
Freescale Semiconductor
Revision
Number
V02.04
V02.05
V02.06
V02.07
Introduction
Revision Date
04 May 2010
26 Aug 2009
1 Jul 2008
9 Jul 2009
14.3.2.12/14-50
14.3.2.13/14-50
14.3.2.16/14-50
14.3.2.12/14-50
14.3.2.13/14-50
14.3.2.15/14-50
14.3.2.16/14-50
14.3.2.19/14-50
14.3.2.15/14-50
14.3.2.2/14-492
14.3.2.3/14-493
14.3.2.4/14-494
14.3.2.8/14-497
14.3.2.11/14-50
14.4.2/14-509
14.4.3/14-509
14.4.2/14-509
14.4.3/14-509
14.1.2/14-486
14.4.3/14-509
14.4.3/14-509
Sections
Affected
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
1
1
4
1
1
3
4
6
3
0
Table 14-1. Revision History
- Revised flag clearing procedure, whereby TEN bit must be set when clearing
flags.
- Revised flag clearing procedure, whereby TEN or PAEN bit must be set
when clearing flags.
- Add fomula to describe prescaler
- Correct typo: TSCR ->TSCR1
- Correct reference: Figure 1-25 -> Figure 1-31
- Add description, “a counter overflow when TTOV[7] is set”, to be the
condition of channel 7 override event.
- Phrase the description of OC7M to make it more explicit
- Add
- in TCRE bit description part,add Note
- Add
Table 14-10
Figure 14-31
Description of Changes
485