S9S12HY64J0MLH Freescale Semiconductor, S9S12HY64J0MLH Datasheet - Page 301

• Manufacturer Part Number: S9S12HY64J0MLH
• Description: MCU 64K FLASH AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLH

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: S12
• No. Of I/o's: 50
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3.2.12
The A/D conversion results are stored in 8 result registers. Results are always in unsigned data
representation. Left and right justification is selected using the DJM control bit in ATDCTL3.
If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must
be written with the compare values in left or right justified format depending on the actual value of the
DJM bit. In this case, as the ATDDRn register is used to hold the compare value, the result will not be
stored there at the end of the conversion but is lost.
Attention, n is the conversion number, NOT the channel number!
Read: Anytime
Write: Anytime
8.3.2.12.1
8.3.2.12.2
Freescale Semiconductor
Module Base +
0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3
0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7
0x0020 = ATDDR8, 0x0022 = ATDDR9
Module Base +
0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3
0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7
0x0020 = ATDDR8, 0x0022 = ATDDR9
Reset
Reset
W
W
R
R
Bit 11 Bit 10 Bit 9
15
15
0
0
0
ATD Conversion Result Registers (ATDDRn)
= Unimplemented or Reserved
= Unimplemented or Reserved
For conversions not using automatic compare, results are stored in the result
registers after each conversion. In this case avoid writing to ATDDRn except
for initial values, because an A/D result might be overwritten.
Left Justified Result Data (DJM=0)
Right Justified Result Data (DJM=1)
14
14
0
0
0
Figure 8-15. Right justified ATD conversion result register (ATDDRn)
Figure 8-14. Left justified ATD conversion result register (ATDDRn)
13
13
0
0
0
Bit 8
12
12
0
0
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Bit 11 Bit 10 Bit 9
Bit 7
11
11
0
0
Bit 6
10
10
0
0
Bit 5
0
0
9
9
NOTE
Bit 4
Bit 8
0
0
8
8
Analog-to-Digital Converter (ADC12B8CV1) Block Description
Bit 3
Bit 7
0
0
7
7
Bit 2
Bit 6
0
0
6
6
Bit 1
Bit 5
0
0
5
5
Bit 0
Bit 4
4
0
4
0
Bit 3
0
0
0
3
3
Bit 2
0
0
0
2
2
Bi1 1
0
0
0
1
1
Bit 0
0
0
0
0
0
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